traffic.tan.qmsg

CPLD开发板VHDL源程序并附上开发板的原理图

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[15\] " "Info: Detected ripple clock \"div_cnt\[15\]\" as buffer" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } } { "d:/program files/win/Assignment Editor.qase" "" { Assignment "d:/program files/win/Assignment Editor.qase" 1 { { 0 "div_cnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } } { "d:/program files/win/Assignment Editor.qase" "" { Assignment "d:/program files/win/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register second\[3\] register second\[0\] 138.68 MHz 7.211 ns Internal " "Info: Clock \"clk\" has Internal fmax of 138.68 MHz between source register \"second\[3\]\" and destination register \"second\[0\]\" (period= 7.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.502 ns + Longest register register " "Info: + Longest register to register delay is 6.502 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second\[3\] 1 REG LC_X4_Y2_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'second\[3\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { second[3] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.914 ns) 1.828 ns Equal1~71 2 COMB LC_X4_Y2_N3 9 " "Info: 2: + IC(0.914 ns) + CELL(0.914 ns) = 1.828 ns; Loc. = LC_X4_Y2_N3; Fanout = 9; COMB Node = 'Equal1~71'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "1.828 ns" { second[3] Equal1~71 } "NODE_NAME" } } { "d:/program files/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.511 ns) 3.787 ns second\[3\]~1099 3 COMB LC_X3_Y2_N8 4 " "Info: 3: + IC(1.448 ns) + CELL(0.511 ns) = 3.787 ns; Loc. = LC_X3_Y2_N8; Fanout = 4; COMB Node = 'second\[3\]~1099'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "1.959 ns" { Equal1~71 second[3]~1099 } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.911 ns) + CELL(0.804 ns) 6.502 ns second\[0\] 4 REG LC_X4_Y2_N1 6 " "Info: 4: + IC(1.911 ns) + CELL(0.804 ns) = 6.502 ns; Loc. = LC_X4_Y2_N1; Fanout = 6; REG Node = 'second\[0\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.715 ns" { second[3]~1099 second[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.229 ns ( 34.28 % ) " "Info: Total cell delay = 2.229 ns ( 34.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.273 ns ( 65.72 % ) " "Info: Total interconnect delay = 4.273 ns ( 65.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "6.502 ns" { second[3] Equal1~71 second[3]~1099 second[0] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "6.502 ns" { second[3] Equal1~71 second[3]~1099 second[0] } { 0.000ns 0.914ns 1.448ns 1.911ns } { 0.000ns 0.914ns 0.511ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.919 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y3_N6 11 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y3_N6; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.277 ns) + CELL(0.918 ns) 7.919 ns second\[0\] 3 REG LC_X4_Y2_N1 6 " "Info: 3: + IC(3.277 ns) + CELL(0.918 ns) = 7.919 ns; Loc. = LC_X4_Y2_N1; Fanout = 6; REG Node = 'second\[0\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "4.195 ns" { div_cnt[24] second[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.62 % ) " "Info: Total cell delay = 3.375 ns ( 42.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.544 ns ( 57.38 % ) " "Info: Total interconnect delay = 4.544 ns ( 57.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[0] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[0] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.919 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y3_N6 11 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y3_N6; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.277 ns) + CELL(0.918 ns) 7.919 ns second\[3\] 3 REG LC_X4_Y2_N4 3 " "Info: 3: + IC(3.277 ns) + CELL(0.918 ns) = 7.919 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'second\[3\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "4.195 ns" { div_cnt[24] second[3] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.62 % ) " "Info: Total cell delay = 3.375 ns ( 42.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.544 ns ( 57.38 % ) " "Info: Total interconnect delay = 4.544 ns ( 57.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[3] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[3] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[0] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[0] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[3] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[3] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "6.502 ns" { second[3] Equal1~71 second[3]~1099 second[0] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "6.502 ns" { second[3] Equal1~71 second[3]~1099 second[0] } { 0.000ns 0.914ns 1.448ns 1.911ns } { 0.000ns 0.914ns 0.511ns 0.804ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[0] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[0] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[3] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[3] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[6\] second\[1\] 16.190 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[6\]\" through register \"second\[1\]\" is 16.190 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.919 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.919 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns div_cnt\[24\] 2 REG LC_X4_Y3_N6 11 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y3_N6; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk div_cnt[24] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.277 ns) + CELL(0.918 ns) 7.919 ns second\[1\] 3 REG LC_X4_Y2_N5 6 " "Info: 3: + IC(3.277 ns) + CELL(0.918 ns) = 7.919 ns; Loc. = LC_X4_Y2_N5; Fanout = 6; REG Node = 'second\[1\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "4.195 ns" { div_cnt[24] second[1] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.62 % ) " "Info: Total cell delay = 3.375 ns ( 42.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.544 ns ( 57.38 % ) " "Info: Total interconnect delay = 4.544 ns ( 57.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[1] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[1] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.895 ns + Longest register pin " "Info: + Longest register to pin delay is 7.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second\[1\] 1 REG LC_X4_Y2_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y2_N5; Fanout = 6; REG Node = 'second\[1\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { second[1] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.317 ns) + CELL(0.914 ns) 2.231 ns data4\[1\]~165 2 COMB LC_X5_Y2_N9 7 " "Info: 2: + IC(1.317 ns) + CELL(0.914 ns) = 2.231 ns; Loc. = LC_X5_Y2_N9; Fanout = 7; COMB Node = 'data4\[1\]~165'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "2.231 ns" { second[1] data4[1]~165 } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.766 ns) + CELL(0.740 ns) 3.737 ns Mux23~17 3 COMB LC_X5_Y2_N2 1 " "Info: 3: + IC(0.766 ns) + CELL(0.740 ns) = 3.737 ns; Loc. = LC_X5_Y2_N2; Fanout = 1; COMB Node = 'Mux23~17'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "1.506 ns" { data4[1]~165 Mux23~17 } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.836 ns) + CELL(2.322 ns) 7.895 ns dataout\[6\] 4 PIN PIN_17 0 " "Info: 4: + IC(1.836 ns) + CELL(2.322 ns) = 7.895 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'dataout\[6\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "4.158 ns" { Mux23~17 dataout[6] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.976 ns ( 50.36 % ) " "Info: Total cell delay = 3.976 ns ( 50.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.919 ns ( 49.64 % ) " "Info: Total interconnect delay = 3.919 ns ( 49.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.895 ns" { second[1] data4[1]~165 Mux23~17 dataout[6] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.895 ns" { second[1] data4[1]~165 Mux23~17 dataout[6] } { 0.000ns 1.317ns 0.766ns 1.836ns } { 0.000ns 0.914ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.919 ns" { clk div_cnt[24] second[1] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.919 ns" { clk clk~combout div_cnt[24] second[1] } { 0.000ns 0.000ns 1.267ns 3.277ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.895 ns" { second[1] data4[1]~165 Mux23~17 dataout[6] } "NODE_NAME" } } { "d:/program files/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/win/Technology_Viewer.qrui" "7.895 ns" { second[1] data4[1]~165 Mux23~17 dataout[6] } { 0.000ns 1.317ns 0.766ns 1.836ns } { 0.000ns 0.914ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 01 21:53:10 2008 " "Info: Processing ended: Sun Jun 01 21:53:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}