traffic.fit.qmsg

来自「CPLD开发板VHDL源程序并附上开发板的原理图」· QMSG 代码 · 共 38 行 · 第 1/3 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.029 ns register pin " "Info: Estimated most critical path is register to pin delay of 7.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns first\[3\] 1 REG LAB_X4_Y2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y2; Fanout = 4; REG Node = 'first\[3\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { first[3] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.740 ns) 1.757 ns data4\[3\]~167 2 COMB LAB_X5_Y2 7 " "Info: 2: + IC(1.017 ns) + CELL(0.740 ns) = 1.757 ns; Loc. = LAB_X5_Y2; Fanout = 7; COMB Node = 'data4\[3\]~167'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "1.757 ns" { first[3] data4[3]~167 } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 2.937 ns Mux26~17 3 COMB LAB_X5_Y2 1 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.937 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux26~17'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "1.180 ns" { data4[3]~167 Mux26~17 } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.770 ns) + CELL(2.322 ns) 7.029 ns dataout\[3\] 4 PIN PIN_41 0 " "Info: 4: + IC(1.770 ns) + CELL(2.322 ns) = 7.029 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dataout\[3\]'" {  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "4.092 ns" { Mux26~17 dataout[3] } "NODE_NAME" } } { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.262 ns ( 46.41 % ) " "Info: Total cell delay = 3.262 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.767 ns ( 53.59 % ) " "Info: Total interconnect delay = 3.767 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "7.029 ns" { first[3] data4[3]~167 Mux26~17 dataout[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 2 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x0_y0 x8_y5 " "Info: The peak interconnect region extends from location x0_y0 to location x8_y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dataout\[0\] VCC " "Info: Pin dataout\[0\] has VCC driving its datain port" {  } { { "traffic.vhd" "" { Text "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd" 14 -1 0 } } { "d:/program files/win/Assignment Editor.qase" "" { Assignment "d:/program files/win/Assignment Editor.qase" 1 { { 0 "dataout\[0\]" } } } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { dataout[0] } "NODE_NAME" } } { "d:/program files/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/win/TimingClosureFloorplan.fld" "" "" { dataout[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 01 21:53:03 2008 " "Info: Processing ended: Sun Jun 01 21:53:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.fit.smsg " "Info: Generated suppressed messages file F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}