traffic.fit.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:6;1:2     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:6;1:2     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1;1:5;2:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1;1:5;2:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:8         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:8         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:6;1:2     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;2:6;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:6;2:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:8         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:7     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:6;1:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:7     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:5;1:3     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:8         ;
; LEs in Chains - Fit Attempt 1                                                  ; 24          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 24          ;
; LABs with Chains - Fit Attempt 1                                               ; 3           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.015       ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Early Slack - Fit Attempt 1         ; -16849 ;
; Mid Wire Use - Fit Attempt 1        ; 5      ;
; Mid Slack - Fit Attempt 1           ; -15511 ;
; Late Wire Use - Fit Attempt 1       ; 5      ;
; Late Slack - Fit Attempt 1          ; -15111 ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.313  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -14058 ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Peak Regional Wire - Fit Attempt 1  ; 2      ;
; Mid Slack - Fit Attempt 1           ; -16160 ;
; Late Slack - Fit Attempt 1          ; -15698 ;
; Late Slack - Fit Attempt 1          ; -15698 ;
; Late Wire Use - Fit Attempt 1       ; 6      ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.062  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 01 21:53:00 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off traffic -c traffic
Info: Selected device EPM240T100C5 for design "traffic"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 24 pins of 24 total pins
    Info: Pin dataout[0] not assigned to an exact location on the device
    Info: Pin dataout[1] not assigned to an exact location on the device
    Info: Pin dataout[2] not assigned to an exact location on the device
    Info: Pin dataout[3] not assigned to an exact location on the device
    Info: Pin dataout[4] not assigned to an exact location on the device
    Info: Pin dataout[5] not assigned to an exact location on the device
    Info: Pin dataout[6] not assigned to an exact location on the device
    Info: Pin dataout[7] not assigned to an exact location on the device
    Info: Pin en[0] not assigned to an exact location on the device
    Info: Pin en[1] not assigned to an exact location on the device
    Info: Pin lightY[0] not assigned to an exact location on the device
    Info: Pin lightY[1] not assigned to an exact location on the device
    Info: Pin lightY[2] not assigned to an exact location on the device
    Info: Pin lightY[3] not assigned to an exact location on the device
    Info: Pin lightG[0] not assigned to an exact location on the device
    Info: Pin lightG[1] not assigned to an exact location on the device
    Info: Pin lightG[2] not assigned to an exact location on the device
    Info: Pin lightG[3] not assigned to an exact location on the device
    Info: Pin lightR[0] not assigned to an exact location on the device
    Info: Pin lightR[1] not assigned to an exact location on the device
    Info: Pin lightR[2] not assigned to an exact location on the device
    Info: Pin lightR[3] not assigned to an exact location on the device
    Info: Pin rst not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted some destinations of signal "div_cnt[24]" to use Global clock
    Info: Destination "div_cnt[24]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "div_cnt[15]" to use Global clock
    Info: Destination "div_cnt[15]" may be non-global or may not use global clock
Info: Automatically promoted signal "rst" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 22 (unused VREF, 3.30 VCCIO, 0 input, 22 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to pin delay of 7.029 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y2; Fanout = 4; REG Node = 'first[3]'
    Info: 2: + IC(1.017 ns) + CELL(0.740 ns) = 1.757 ns; Loc. = LAB_X5_Y2; Fanout = 7; COMB Node = 'data4[3]~167'
    Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.937 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux26~17'
    Info: 4: + IC(1.770 ns) + CELL(2.322 ns) = 7.029 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dataout[3]'
    Info: Total cell delay = 3.262 ns ( 46.41 % )
    Info: Total interconnect delay = 3.767 ns ( 53.59 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin dataout[0] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jun 01 21:53:03 2008
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.fit.smsg.