traffic.map.rpt

CPLD开发板VHDL源程序并附上开发板的原理图

; traffic.vhd                      ; yes             ; User VHDL File  ; F:/学习文件/EDA/CPLD开发板VHDL源程序并附上开发板的原理图/VHDL_Development_Board_Sources/综合实验/交通灯/traffic/traffic.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 66    ;
;     -- Combinational with no register       ; 29    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 37    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 24    ;
;     -- 3 input functions                    ; 10    ;
;     -- 2 input functions                    ; 29    ;
;     -- 1 input functions                    ; 3     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 43    ;
;     -- arithmetic mode                      ; 23    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 3     ;
;     -- asynchronous clear/load mode         ; 37    ;
;                                             ;       ;
; Total registers                             ; 37    ;
; Total logic cells in carry chains           ; 24    ;
; I/O pins                                    ; 24    ;
; Maximum fan-out node                        ; rst   ;
; Maximum fan-out                             ; 37    ;
; Total fan-out                               ; 287   ;
; Average fan-out                             ; 3.19  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |traffic                   ; 66 (66)     ; 37           ; 0          ; 24   ; 0            ; 29 (29)      ; 0 (0)             ; 37 (37)          ; 24 (24)         ; 0 (0)      ; |traffic            ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 37    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 3     ;
; Number of registers using Asynchronous Clear ; 37    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; en_xhdl[1]                             ; 6       ;
; second[0]                              ; 6       ;
; second[1]                              ; 6       ;
; Total number of inverted registers = 3 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 7:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |traffic|second[3]         ;
; 9:1                ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |traffic|state[0]          ;
; 9:1                ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |traffic|first[1]          ;
; 9:1                ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |traffic|first[3]          ;
; 10:1               ; 2 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |traffic|second[1]         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 01 21:52:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 2 design units, including 1 entities, in source file traffic.vhd
    Info: Found design unit 1: traffic-arch
    Info: Found entity 1: traffic
Info: Elaborating entity "traffic" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dataout[0]" stuck at VCC
Info: Registers with preset signals will power-up high
Info: Implemented 90 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 22 output pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Jun 01 21:52:58 2008
    Info: Elapsed time: 00:00:03