jamcpudoc.ps

jam CPU模拟器的设计与实现.其中包含设计文档

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107.72 53.86 524.41 53.86 2 L
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(Concert\32502 Architecture Speci\336cation and Implementation) 107.72 42.86 T
(22 March 2002) 298.71 42.86 T
(1) 520.41 42.86 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
0 24 Q
(Concert\32502) 262.08 755.02 T
(Architecture Speci\336cation) 190.42 725.02 T
(and Implementation) 219.74 695.02 T
1 12 Q
(J) 258.13 655.02 T
(ohan Eriksson Thelin) 263.95 655.02 T
(Anders Lindstr\232m) 268.56 639.02 T
(Michael Nordseth) 270.23 623.02 T
(Chalmers Uni) 225.91 591.02 T
(v) 297.45 591.02 T
(ersity of T) 303.33 591.02 T
(echnology) 354.88 591.02 T
( 2002) 302.56 575.02 T
1 16 Q
(Abstract) 107.72 532.36 T
0 12 Q
(This document describes a RISC CPU architecture, Concert\32502. The Concert\32502 archi-) 107.72 505.02 T
(tecture is based on an older speci\336cation, b) 107.72 491.02 T
(ut has been updated for the intended host) 314.1 491.02 T
(system.) 107.72 477.02 T
-0.22 (W) 107.72 451.02 P
-0.22 (e continue by implementing the architecture in VHDL. The implementation is called) 118.08 451.02 P
-0.11 (the J) 107.72 437.02 P
-0.11 (AM CPU core. It is a \336v) 129.22 437.02 P
-0.11 (e-stage pipe-lined CPU core, with multi-c) 246.04 437.02 P
-0.11 (ycle operations,) 445.95 437.02 P
(forw) 107.72 423.02 T
(arding and hazard checking.) 130.25 423.02 T
(The CPU has been tested in an actual FPGA, and pro) 107.72 397.02 T
(v) 362.5 397.02 T
(ed to w) 368.32 397.02 T
(ork properly) 403.53 397.02 T
(. W) 462.4 397.02 T
(e ha) 478.77 397.02 T
(v) 498.18 397.02 T
(e) 504 397.02 T
(analysed the critical path, the synthesis timing and area report and current perform-) 107.72 383.02 T
(ance.) 107.72 369.02 T
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107.72 53.86 524.41 53.86 2 L
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0 8 Q
(Concert\32502 Architecture Speci\336cation and Implementation) 107.72 42.86 T
(22 March 2002) 298.71 42.86 T
(2) 520.41 42.86 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
1 16 Q
(1.0  T) 107.72 760.36 T
(able of Contents) 144.92 760.36 T
0 12 Q
(1.0) 107.72 737.02 T
(T) 144.57 737.02 T
(able of Contents) 150.94 737.02 T
(...........................................................................................) 231 737.02 T
(2) 504.24 737.02 T
(2.0) 107.72 717.02 T
(The Concert\32502 Architecture Speci\336cation) 144.57 717.02 T
(...................................................) 351 717.02 T
(3) 504.24 717.02 T
0 10 Q
(2.1) 144.57 702.36 T
(System Ov) 178.58 702.36 T
(ervie) 222.6 702.36 T
(w) 242.34 702.36 T
(......................................................................................................) 250 702.36 T
(3) 505.24 702.36 T
(2.1.1) 178.58 690.36 T
(The T) 215.43 690.36 T
(imer and Syncronisation Unit) 239.24 690.36 T
(...........................................................) 357.5 690.36 T
(3) 505.24 690.36 T
(2.1.2) 178.58 678.36 T
(The I/O Unit) 215.43 678.36 T
(...............................................................................................) 267.5 678.36 T
(4) 505.24 678.36 T
(2.1.3) 178.58 666.36 T
(Memory Layout) 215.43 666.36 T
(.........................................................................................) 282.5 666.36 T
(4) 505.24 666.36 T
(2.2) 144.57 652.36 T
(Programming Model) 178.58 652.36 T
(.................................................................................................) 262.5 652.36 T
(5) 505.24 652.36 T
(2.2.1) 178.58 640.36 T
(Datatypes) 215.43 640.36 T
(...................................................................................................) 257.5 640.36 T
(5) 505.24 640.36 T
(2.2.2) 178.58 628.36 T
(V) 215.43 628.36 T
(isible State V) 222.05 628.36 T
(ariables) 274.83 628.36 T
(...............................................................................) 307.5 628.36 T
(5) 505.24 628.36 T
(2.3) 144.57 614.36 T
(Instruction Set and Encoding) 178.58 614.36 T
(....................................................................................) 295 614.36 T
(6) 505.24 614.36 T
(2.3.1) 178.58 602.36 T
(T) 215.43 602.36 T
(raps, Interrupts and Initialisation) 221.19 602.36 T
(.............................................................) 352.5 602.36 T
(9) 505.24 602.36 T
(2.4) 144.57 588.36 T
(Changes from the Original Concert Speci\336cation) 178.58 588.36 T
(..................................................) 375 588.36 T
(10) 500.24 588.36 T
(2.4.1) 178.58 576.36 T
(Instruction set modi\336cations) 215.43 576.36 T
(....................................................................) 330 576.36 T
(10) 500.24 576.36 T
(2.4.2) 178.58 564.36 T
(Memory layout modi\336cations) 215.43 564.36 T
(..................................................................) 335 564.36 T
(10) 500.24 564.36 T
(2.4.3) 178.58 552.36 T
(System en) 215.43 552.36 T
(vironment modi\336cations) 256.42 552.36 T
(..........................................................) 355 552.36 T
(10) 500.24 552.36 T
0 12 Q
(3.0) 107.72 533.02 T
(Project Goals) 144.57 533.02 T
(................................................................................................) 210 533.02 T
(10) 498.24 533.02 T
(4.0) 107.72 513.02 T
(Ov) 144.57 513.02 T
(ervie) 159.05 513.02 T
(w of the Concert\32502 Implementation) 182.74 513.02 T
(..............................................) 360 513.02 T
(11) 498.24 513.02 T
0 10 Q
(4.1) 144.57 498.36 T
(The CPU System En) 178.58 498.36 T
(vironment) 261.24 498.36 T
(...............................................................................) 302.5 498.36 T
(11) 500.24 498.36 T
(4.1.1) 178.58 486.36 T
(The T) 215.43 486.36 T
(imer) 239.24 486.36 T
(................................................................................................) 260 486.36 T
(11) 500.24 486.36 T
(4.1.2) 178.58 474.36 T
(The RESET Generation Logic) 215.43 474.36 T
(.................................................................) 337.5 474.36 T
(12) 500.24 474.36 T
(4.2) 144.57 460.36 T
(Ov) 178.58 460.36 T
(ervie) 190.65 460.36 T
(w of the CPU Core) 210.39 460.36 T
(.....................................................................................) 287.5 460.36 T
(12) 500.24 460.36 T
(4.2.1) 178.58 448.36 T
(The CPU Core Pipe-line) 215.43 448.36 T
(..........................................................................) 315 448.36 T
(14) 500.24 448.36 T
(4.2.2) 178.58 436.36 T
(IF) 215.43 436.36 T
(..............................................................................................................) 225 436.36 T
(15) 500.24 436.36 T
(4.2.3) 178.58 424.36 T
(ID) 215.43 424.36 T
(.............................................................................................................) 227.5 424.36 T
(15) 500.24 424.36 T
(4.2.4) 178.58 412.36 T
(EX) 215.43 412.36 T
(............................................................................................................) 230 412.36 T
(16) 500.24 412.36 T
(4.2.5) 178.58 400.36 T
(MEM) 215.43 400.36 T
(........................................................................................................) 240 400.36 T
(21) 500.24 400.36 T
(4.2.6) 178.58 388.36 T
(WB) 215.43 388.36 T
(...........................................................................................................) 232.5 388.36 T
(23) 500.24 388.36 T
(4.2.7) 178.58 376.36 T
(F) 215.43 376.36 T
(orw) 220.84 376.36 T
(arding and Hazard Checking) 236.29 376.36 T
(...........................................................) 352.5 376.36 T
(24) 500.24 376.36 T
(4.2.8) 178.58 364.36 T
(T) 215.43 364.36 T
(raps and Interrupts) 221.19 364.36 T
(.................................................................................) 297.5 364.36 T
(27) 500.24 364.36 T
(4.3) 144.57 350.36 T
(Design Choices and Performance) 178.58 350.36 T
(...........................................................................) 312.5 350.36 T
(27) 500.24 350.36 T
(4.3.1) 178.58 338.36 T
(T) 215.43 338.36 T
(esting) 220.84 338.36 T
(......................................................................................................) 245 338.36 T
(27) 500.24 338.36 T
(4.3.2) 178.58 326.36 T
(Design Choices) 215.43 326.36 T
(........................................................................................) 280 326.36 T
(28) 500.24 326.36 T
(4.3.3) 178.58 314.36 T
(Performance) 215.43 314.36 T
(.............................................................................................) 267.5 314.36 T
(31) 500.24 314.36 T
0 12 Q
(5.0) 107.72 295.02 T
(Synthesis of the J) 144.57 295.02 T
(AM CPU Core) 228.18 295.02 T
(.................................................................) 303 295.02 T
(36) 498.24 295.02 T
0 10 Q
(5.1) 144.57 280.36 T
(Xilinx V) 178.58 280.36 T
(irte) 213.26 280.36 T
(x XCV300) 226.44 280.36 T
(...........................................................................................) 272.5 280.36 T
(36) 500.24 280.36 T
(5.1.1) 178.58 268.36 T
(Performance Summary) 215.43 268.36 T
(............................................................................) 310 268.36 T
(36) 500.24 268.36 T
(5.1.2) 178.58 256.36 T
(Resource Usage Report) 215.43 256.36 T
(............................................................................) 310 256.36 T
(36) 500.24 256.36 T
(5.2) 144.57 242.36 T
(Xilinx V) 178.58 242.36 T
(irte) 213.26 242.36 T
(x2 XC2V3000) 226.44 242.36 T
(.....................................................................................) 287.5 242.36 T
(36) 500.24 242.36 T
(5.2.1) 178.58 230.36 T
(Performance Summary) 215.43 230.36 T
(............................................................................) 310 230.36 T
(36) 500.24 230.36 T
(5.2.2) 178.58 218.36 T
(Resource Usage Report) 215.43 218.36 T
(............................................................................) 310 218.36 T
(36) 500.24 218.36 T
(5.3) 144.57 204.36 T
(Altera MERCUR) 178.58 204.36 T
(Y EP1M350) 247.65 204.36 T
(................................................................................) 300 204.36 T
(37) 500.24 204.36 T
(5.3.1) 178.58 192.36 T
(Performance Summary) 215.43 192.36 T
(............................................................................) 310 192.36 T
(37) 500.24 192.36 T
(5.3.2) 178.58 180.36 T
(Resource Usage Report) 215.43 180.36 T
(............................................................................) 310 180.36 T
(37) 500.24 180.36 T
0 12 Q
(6.0) 107.72 161.02 T
(Conclusions) 144.57 161.02 T
(..................................................................................................) 204 161.02 T
(37) 498.24 161.02 T
(7.0) 107.72 141.02 T
(References) 144.57 141.02 T
(....................................................................................................) 198 141.02 T
(37) 498.24 141.02 T
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107.72 53.86 524.41 53.86 2 L
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(Concert\32502 Architecture Speci\336cation and Implementation) 107.72 42.86 T
(22 March 2002) 298.71 42.86 T
(3) 520.41 42.86 T
0 0 0 1 0 0 0 K
0 0 0 1 0 0 0 K
1 16 Q
(2.0  The Concert\32502 Ar) 107.72 760.36 T
(chitectur) 265.17 760.36 T
(e Speci\336cation) 326.2 760.36 T
0 12 Q
-0.08 (This chapter co) 107.72 733.02 P
-0.08 (v) 181.36 733.02 P
-0.08 (ers the Concert\32502 computer architecture. Concert\32502 is an adaptation) 187.18 733.02 P
(of the Concert architecture [1] for an FPGA system. It describes a 32 bits RISC archi-) 107.72 719.02 T
(tecture with precise interrupts.) 107.72 705.02 T
(The changes that ha) 107.72 679.02 T
(v) 203.12 679.02 T
(e been made can be di) 208.94 679.02 T
(vided into the follo) 314.93 679.02 T
(wing cate) 406.3 679.02 T
(gories:) 452.44 679.02 T
2 F
(\245) 107.72 659.02 T
0 F
(Instruction set modi\336cations) 121.89 659.02 T
2 F
(\245) 107.72 639.02 T
0 F
(Memory layout modi\336cations) 121.89 639.02 T
2 F
(\245) 107.72 619.02 T
0 F
(System en) 121.89 619.02 T
(vironment modi\336cations) 171.08 619.02 T
(These changes are all discussed in detail in chapter 2.4.) 107.72 593.02 T
1 14 Q
(2.1  System Ov) 107.72 559.69 T
(er) 196.24 559.69 T
(view) 208.53 559.69 T
0 12 Q
(The Concert\32502 system architecture can be seen in \336gure 1. It features four units out-) 107.72 533.02 T
(side the CPU core, the T) 107.72 519.02 T
(imer and Syncronisation Unit, STU, the I/O unit and the tw) 225.28 519.02 T
(o) 509.81 519.02 T
(memories, IM and DM. The I/O unit has been left out as our lab system \050see chapter) 107.72 505.02 T
(4.1\051 does not support parallell I/O to the outside w) 107.72 491.02 T
(orld.) 349.58 491.02 T
(Communication between the CPU core and the units STU and I/O is handled through) 107.72 465.02 T
-0.24 (the PUT signal \050described in chapter 2.1.2\051, the SYNCTRAP signal \050described in chap-) 107.72 451.02 P
(ter 2.1.1\051 and the processor status w) 107.72 437.02 T
(ord, PSW) 280.23 437.02 T
(, which is described in detail in chapter) 325.79 437.02 T
(2.2.2.) 107.72 423.02 T
1 10 Q
(FIGURE 1. System Ov) 121.89 398.36 T
(er) 219.01 398.36 T
(view) 227.79 398.36 T
1 12 Q
(2.1.1  The T) 107.72 211.02 T
(imer and Syncr) 168.51 211.02 T
(onisation Unit) 247.62 211.02 T
0 F
(The STU manages the SYNCTRAP signal and the interrupt timer) 107.72 185.02 T
(. The  SYNCTRAP) 422.03 185.02 T
-0.2 (signal is used to indicate that an e) 107.72 171.02 P
-0.2 (xternal interrupt has occured. This is indicated by set-) 267.76 171.02 P
(ting the signal high during one clock c) 107.72 157.02 T
(ycle.) 291.86 157.02 T
(The interrupt timer