dac5662_top.vhd

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-- ###########################################################################
-- Module:  DAC5662_TOP
-- Description:  
-- This module for DAC5662.

-- Designed by:  Ahrong
-- E-mail: [e-mail]
-- Revision History:
--   1.0  2005-12-28  Ahrong
--        Initial version

-- End
-- ###########################################################################

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DAC5662_TOP is
    port (
         -- System signals
         CLK	            : in STD_LOGIC;         --System clock, 33MHZ
         RST               : in STD_LOGIC;         --Reset
         DAC5662_START     : in STD_LOGIC := '0';  -- it must be active for one SCLK
         DAC5662_DIN       : in STD_LOGIC_VECTOR(31 downto 0);	

         DAC5662_SCLK      : out STD_LOGIC;        --  DAC5562 SPI clock
         DAC5662_FSYNC_N   : out STD_LOGIC;        --  DAC5562 component select ,low active
         DAC5662_SDOUT     : out STD_LOGIC         --  Data of the DAC5562 SPI
         );
end DAC5662_TOP;

architecture Behavioral of DAC5662_TOP is

	component dac5662_clock
	port(
		CLK         : in   std_logic;          
		SCLK_RISE   : out std_logic;
		SCLK_FALL   : out std_logic
		);
	end component;

	component dac5662_spi
	port(
		CLK         : in std_logic;
		RST         : in std_logic;
		SCLK_RISE   : in std_logic;
		SCLK_FALL   : in std_logic;
		DAC_DIN     : in std_logic_vector(15 downto 0);
		DAC_EN      : in std_logic;          
		DAC_FINISH  : out std_logic;
		DAC_SCLK    : out std_logic;
		DAC_SYNC_N  : out std_logic;
		DAC_DO      : out std_logic
		);
	end component;

     component DAC5662_POLLING 
     port (
         -- System signals
         CLK	        : in std_logic;        
         RST           : in STD_LOGIC;
         SCLK_RISE     : in STD_LOGIC;
         SCLK_FALL     : in STD_LOGIC;
         DAC_START     : in std_logic := '0'; 
         DAC_D0        : in STD_LOGIC_VECTOR(15 downto 0);
         DAC_DATA      : out STD_LOGIC_VECTOR(15 downto 0);
         DAC_EN        : out STD_LOGIC;   
         DAC_FINISH    : in  STD_LOGIC    
         );
	 end component;


signal SCLK_RISE   :  std_logic;
signal SCLK_FALL   :  std_logic;
signal DAC_DIN     :  std_logic_vector(15 downto 0) :="0000000000000000";
signal DAC_POLL    :  std_logic_vector(15 downto 0) :="0000000000000000";    
signal DAC_EN      :  std_logic;
signal DAC_FINISH  :  std_logic;
signal DAC_START   :  std_logic:='0';
signal DIN_OLD     :  std_logic_vector(31 downto 0) :="00000000000000000000000000000000";
signal DIN_NEW     :  std_logic_vector(31 downto 0) :="00000000000000000000000000000000";


signal flg_INITIAL1_FINISH : std_logic  :='0';
signal flg_READDATA_FINISH  : std_logic  :='0';
signal flg_DAC5662_DIN	  : std_logic  :='0';


subtype state is std_logic_vector(3 downto 0);
signal   STATE_CS  : state;
constant IDLE      : state   := "0001";
constant INITIAL1  : state   := "0010";
constant READREADY : state   := "0100";
constant READDATA  : state   := "1000";


-- INITIAL DATA
--constant regInitial1 : std_logic_vector(15 downto 0) :="0100000000000000";	
constant regInitial1 : std_logic_vector(15 downto 0) :="0000000111110100";	
signal state_IDLE       : std_logic;
signal state_INITIAL1   : std_logic;
signal state_READREADY  : std_logic;
signal state_READDATA   : std_logic;





begin

	U_CLOCK: dac5662_clock 
   port map(
		CLK         => CLK,
		SCLK_RISE   => SCLK_RISE,
		SCLK_FALL   => SCLK_FALL
	);

	U_SPI: dac5662_spi 
   port map(
		CLK         => CLK,
		RST         => RST,
		SCLK_RISE   => SCLK_RISE,
		SCLK_FALL   => SCLK_FALL,
		DAC_DIN     => DAC_POLL,
		DAC_EN      => DAC_EN,
		DAC_FINISH  => DAC_FINISH,
		DAC_SCLK    => DAC5662_SCLK,
		DAC_SYNC_N  => DAC5662_FSYNC_N,
		DAC_DO      => DAC5662_SDOUT
	);

      U_DAC_POLLING: DAC5662_POLLING 
    port map (
		CLK          => CLK,
		RST          => RST,
		SCLK_RISE    => SCLK_RISE,
		SCLK_FALL    => SCLK_FALL,
          DAC_START    => DAC_START,
          DAC_D0       => DAC_POLL, 
		DAC_DATA     => DAC_DIN,
          DAC_EN       => DAC_EN,
          DAC_FINISH   => DAC_FINISH
         );


     state_IDLE      <= STATE_CS(0);
     state_INITIAL1  <= STATE_CS(1);
     state_READREADY <= STATE_CS(2);
     state_READDATA  <= STATE_CS(3);



 	process(RST,CLK) --flg_DAC5662_DIN
	begin
  	if RST = '1' then
	   flg_DAC5662_DIN <= '1';
     elsif rising_edge(CLK) and (SCLK_FALL = '1')   then
             if DIN_OLD = DIN_NEW then
		      flg_DAC5662_DIN <= '1';
             else
                flg_DAC5662_DIN <= '0';
             end if;
     end if;
	end process;


--DAC5662 FSM
process(RST,CLK)
begin
   if RST = '1' then
      STATE_CS <= IDLE;
   elsif rising_edge(CLK) and (SCLK_FALL = '1') then
      case STATE_CS is
         when IDLE =>
            if DAC5662_START = '1' then
              STATE_CS <= INITIAL1;
            end if;
         when INITIAL1 =>
            if flg_INITIAL1_FINISH = '1' then
              STATE_CS <= READREADY;
            end if;
         when READREADY =>
            if flg_DAC5662_DIN = '1' then
               STATE_CS <= READREADY;
            else
		     STATE_CS <= READDATA;
            end if;
         when READDATA =>
            if flg_READDATA_FINISH = '1' then
               STATE_CS <= READREADY;
            end if;            
         when others	=>
         	     STATE_CS	<= IDLE;
      end case;
   end if;
end process;




process(CLK)
begin														
   if rising_edge(CLK) and (SCLK_FALL = '1') then
      if state_INITIAL1 = '1'  then
     	   DAC_START <= '1';
		     DAC_POLL  <= regInitial1;
		     if DAC_FINISH = '1'	then
			   flg_INITIAL1_FINISH <= '1';
			   DAC_START <= '0'; 
			else
			   flg_INITIAL1_FINISH <= '0';
               end if;
	  end if;

	  if state_READREADY = '1'  then
	        DIN_NEW <= DAC5662_DIN;
		   DAC_START <= '0';
	  end if;

	  if state_READDATA = '1'  then
             DAC_START <= '1';
		   DAC_POLL  <=  DIN_NEW(15 downto 0);
		   if DAC_FINISH = '1'	then
		      flg_READDATA_FINISH <= '1';
			 DAC_START <= '0'; 
		   else
			 flg_READDATA_FINISH <= '0';
             end if;
		   DIN_OLD <= DIN_NEW;
	  end if;
	      
   end if;
end process;

end Behavioral;