dac5662_clock.vhd

好东西

-- ###########################################################################
-- Module:  DAC_CLOCK
-- Description:  
-- This module generates low frequency clock for DAC control.

-- Designed by:  Ahrong
-- E-mail: [e-mail]
-- Revision History:
--   1.0  2005-12-28  Ahrong
--        Initial version

-- End
-- ###########################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity DAC5662_CLOCK is
    port (
         -- System signals
         CLK	        : in std_logic; --System clock, 33MHZ

         --CLOCK FOR DAC LOGIC, 4M Hz
         SCLK_RISE     : OUT STD_LOGIC; 
         SCLK_FALL     : OUT STD_LOGIC
         );

end DAC5662_CLOCK;

architecture Behavioral of DAC5662_CLOCK is

   signal   pull_hi   : std_logic;
   signal   pull_lo   : std_logic;
   signal   reg_D1    : std_logic;
--   signal   reg_D2    : std_logic;

   component SRL16E_1    --falling edge triggered
      -- | Nonesynthesis (translate)_off 
          generic (INIT: bit_vector := X"0001"); 
      -- | Nonesynthesis (translate)_on 
      port (Q : out STD_ULOGIC; 
            A0 : in STD_ULOGIC; 
            A1 : in STD_ULOGIC; 
            A2 : in STD_ULOGIC; 
            A3 : in STD_ULOGIC; 
            CE : in STD_ULOGIC; 
            CLK : in STD_ULOGIC; 
            D : in STD_ULOGIC); 
   end component; 

begin

   pull_hi <= '1';
   pull_lo <= '0';

   -- clock enable signal for 4Mhz
   U1_8M : SRL16E_1 
   -- | Nonesynthesis (translate)_off 
   generic map (INIT => X"0001") 
   -- | Nonesynthesis (translate)_on 
   port map (Q   => reg_D1, 
             A0  => pull_hi, 
             A1  => pull_hi, 
             A2  => pull_hi, 
             A3  => pull_lo, 
             CE  => pull_hi, 
             CLK => CLK, 
             D   => reg_D1); 
  
  SCLK_RISE <=  reg_D1;

   U2_delay : SRL16E_1 
   -- | Nonesynthesis (translate)_off 
   generic map (INIT => X"0000") 
   -- | Nonesynthesis (translate)_on 
   port map (Q   => SCLK_FALL, 
             A0  => pull_hi, 
             A1  => pull_hi, 
             A2  => pull_lo, 
             A3  => pull_lo, 
             CE  => pull_hi, 
             CLK => CLK, 
             D   => reg_D1); 

end Behavioral;