dac5662_polling.vhd

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-- ###########################################################################

-- Module:  DAC_LOOP
-- Description:  
-- This module pollings all four channels of DAC registers and enable the DAC accordingly.

-- Designed by:  Ahrong
-- E-mail: [e-mail]
-- Revision History:
--   1.0  2005-12-28  Ahrong
--        Initial version

-- End
-- ###########################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC5662_POLLING is
    port (
         -- System signals
         CLK	        : in std_logic; --System clock, 33MHZ
         RST           : IN STD_LOGIC;

         -- signals to/from other modules
         SCLK_RISE     : IN STD_LOGIC; --CLOCK FOR DAC SPI
         SCLK_FALL     : IN STD_LOGIC;

         DAC_START     : in std_logic := '0';  -- it must be active for one SCLK
         DAC_D0        : IN STD_LOGIC_VECTOR(15 DOWNTO 0);

         DAC_DATA      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
         DAC_EN        : OUT STD_LOGIC;   -- active till DAC_FINISH asserted
         DAC_FINISH    : IN  STD_LOGIC    --  indecates the completion of the DAC SPI
         );

end DAC5662_POLLING;


architecture Behavioral of DAC5662_POLLING is

subtype state is std_logic_vector(2 downto 0);
signal   STATE_CS : state;
constant IDLE     : state   := "001";
constant READY    : state   := "010";
constant DAC_S0   : state   := "100";

signal state_IDLE : std_logic;
signal state_READY : std_logic;
signal state_DAC_S0 : std_logic;

signal reg_DACs_ENABLE : std_logic;

begin

state_IDLE    <= STATE_CS(0);
state_READY   <= STATE_CS(1);
state_DAC_S0  <= STATE_CS(2);

--Polling FSM
process(RST,CLK)
begin
   if RST = '1' then
      STATE_CS <= IDLE;
   elsif rising_edge(CLK) and (SCLK_FALL = '1') then
      case STATE_CS is
         when IDLE =>
            if DAC_START = '1' then
              STATE_CS <= READY;
            end if;
         when READY =>
            STATE_CS <= DAC_S0;

         when DAC_S0 =>
            if DAC_FINISH = '1' or reg_DACs_ENABLE = '0' THEN
               STATE_CS <= IDLE;
            END IF;
         when others	=>
         	STATE_CS	<= IDLE;
      end case;
   end if;
end process;

-- to register the enable signals
process(RST,CLK)
begin
   if RST = '1' then
      reg_DACs_ENABLE <= '0';
   elsif rising_edge(CLK) and (SCLK_FALL = '1') then
      if state_READY = '1' then
         reg_DACs_ENABLE <= DAC_START ;
      end if;
   end if;   
end process;

-- To check dac_enable
DAC_EN <= reg_DACs_ENABLE  when state_DAC_S0 = '1' else
          '0';  

-- to determine DAC value
DAC_DATA <= DAC_D0  when state_DAC_S0 = '1' else
            (others => '0');

end Behavioral;