txdsubsys.vhd

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-- -------------------------------------------------------------
--
-- File Name: hdlsrc\TxDSubsys.vhd
-- Created: 2008-12-05 10:47:49
-- Generated by MATLAB 7.6 and Simulink HDL Coder 1.3
--
--
-- -------------------------------------------------------------


-- -------------------------------------------------------------
--
-- Module: TxDSubsys
-- Source Path: MyUART1/TxDSubsys
-- Hierarchy Level: 0
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY TxDSubsys IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        clk_enable                        :   IN    std_logic;
        TxDData                           :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
        Ready                             :   IN    std_logic;  -- ufix1
        ce_out                            :   OUT   std_logic;
        TxD                               :   OUT   std_logic;  -- ufix1
        Wr                                :   OUT   std_logic  -- ufix1
        );
END TxDSubsys;


ARCHITECTURE rtl OF TxDSubsys IS

  -- Component Declarations
  COMPONENT TxdChart
    PORT( clk                             :   IN    std_logic;
          clk_enable                      :   IN    std_logic;
          reset                           :   IN    std_logic;
          TxDData                         :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
          Ready                           :   IN    std_logic;  -- ufix1
          TxD                             :   OUT   std_logic;  -- ufix1
          Wr                              :   OUT   std_logic  -- ufix1
          );
  END COMPONENT;

  -- Component Configuration Statements
  FOR ALL : TxdChart
    USE ENTITY work.TxdChart(fsm_SFHDL);

  -- Signals
  SIGNAL enb                              : std_logic;
  SIGNAL enb_1_1_1                        : std_logic;
  SIGNAL TxdChart_out1                    : std_logic;  -- ufix1
  SIGNAL TxdChart_out2                    : std_logic;  -- ufix1

BEGIN
  u_TxdChart : TxdChart
    PORT MAP
      (clk => clk,
       clk_enable => enb,
       reset => reset,
       TxDData => TxDData,  -- uint8
       Ready => Ready,  -- ufix1
       TxD => TxdChart_out1,  -- ufix1
       Wr => TxdChart_out2  -- ufix1
       );
  enb_1_1_1 <= clk_enable;

  ce_out <= enb_1_1_1;

  enb <= clk_enable;

  TxD <= TxdChart_out1;

  Wr <= TxdChart_out2;

END rtl;