txdchart.vhd

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-------------------------------------------------------------------
-- Stateflow HDL code generation for chart:
--    MyUART1/TxDSubsys/TxdChart
-- 
-- Target language                      : vhdl
-- Date of code generation              : 05-Dec-2008 10:47:49
--
-- Entity name                          : TxdChart
-- Register output                      : ON
-- Clock name                           : clk
-- Clock_enable name                    : clk_enable
-- Reset name                           : reset
-- Reset type                           : Asynchronous
-------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY TxdChart IS
    PORT (
        clk : IN std_logic; 
        clk_enable : IN std_logic; 
        reset : IN std_logic;
        TxDData : IN std_logic_vector(7 DOWNTO 0);
        Ready : IN std_logic;
        TxD : OUT std_logic;
        Wr : OUT std_logic);
END TxdChart;


ARCHITECTURE fsm_SFHDL OF TxdChart IS

    TYPE T_state_type_is_CntPro is (IN_NO_ACTIVE_CHILD, IN_DEC, IN_Last, IN_WAIT);
    TYPE T_state_type_is_TxdPro is (IN_NO_ACTIVE_CHILD, IN_DATA, IN_DELAY2, IN_Delay, IN_IDLE, IN_START, IN_STOP);
    SIGNAL is_CntPro : T_state_type_is_CntPro;
    SIGNAL is_TxdPro : T_state_type_is_TxdPro;
    SIGNAL Tmp : unsigned(7 DOWNTO 0);
    SIGNAL BitCnt : unsigned(3 DOWNTO 0);
    SIGNAL RateCnt : unsigned(4 DOWNTO 0);
    SIGNAL TxD_reg : std_logic;
    SIGNAL Wr_reg : std_logic;
    SIGNAL is_CntPro_next : T_state_type_is_CntPro;
    SIGNAL is_TxdPro_next : T_state_type_is_TxdPro;
    SIGNAL Tmp_next : unsigned(7 DOWNTO 0);
    SIGNAL BitCnt_next : unsigned(3 DOWNTO 0);
    SIGNAL RateCnt_next : unsigned(4 DOWNTO 0);
    SIGNAL TxD_reg_next : std_logic;
    SIGNAL Wr_reg_next : std_logic;

BEGIN
    initialize_TxdChart : PROCESS (reset, clk)
        -- local variables
    BEGIN
        IF reset = '1' THEN
            Tmp <= to_unsigned(0, 8);
            is_TxdPro <= IN_IDLE;
            BitCnt <= to_unsigned(0, 4);
            TxD_reg <= '1';
            Wr_reg <= '0';
            is_CntPro <= IN_WAIT;
            RateCnt <= to_unsigned(15, 5);
        ELSIF clk'EVENT AND clk= '1' THEN
            IF clk_enable= '1' THEN
                is_CntPro <= is_CntPro_next;
                is_TxdPro <= is_TxdPro_next;
                Tmp <= Tmp_next;
                BitCnt <= BitCnt_next;
                RateCnt <= RateCnt_next;
                TxD_reg <= TxD_reg_next;
                Wr_reg <= Wr_reg_next;
            END IF;
        END IF;
    END PROCESS initialize_TxdChart;

    TxdChart : PROCESS (TxDData, Ready, is_CntPro, is_TxdPro, Tmp, BitCnt, RateCnt, TxD_reg, Wr_reg)
        -- local variables
        VARIABLE BitCnt_temp : unsigned(3 DOWNTO 0);
    BEGIN
        is_CntPro_next <= is_CntPro;
        is_TxdPro_next <= is_TxdPro;
        Tmp_next <= Tmp;
        RateCnt_next <= RateCnt;
        TxD_reg_next <= TxD_reg;
        Wr_reg_next <= Wr_reg;
        BitCnt_temp := BitCnt;

        CASE is_TxdPro IS
            WHEN IN_DATA =>

                IF RateCnt = 0 THEN 
                    is_TxdPro_next <= IN_Delay;
                    BitCnt_temp := BitCnt + 1;
                END IF;

            WHEN IN_DELAY2 =>

                IF RateCnt = 0 THEN 
                    is_TxdPro_next <= IN_DATA;
                    -- 2;
                    TxD_reg_next <= Tmp(0);
                    Tmp_next <= SHIFT_RIGHT(Tmp , 1);
                END IF;

            WHEN IN_Delay =>

                IF BitCnt = 8 THEN 
                    is_TxdPro_next <= IN_STOP;
                    TxD_reg_next <= '1';
                    BitCnt_temp := to_unsigned(9, 4);
                ELSE 
                    is_TxdPro_next <= IN_DATA;
                    -- 2;
                    TxD_reg_next <= Tmp(0);
                    Tmp_next <= SHIFT_RIGHT(Tmp , 1);
                END IF;

            WHEN IN_IDLE =>

                IF Ready = '1' THEN 
                    Tmp_next <= unsigned(TxDData);
                    Wr_reg_next <= '1';
                    is_TxdPro_next <= IN_START;
                    TxD_reg_next <= '0';
                ELSE 
                    is_TxdPro_next <= IN_IDLE;
                    BitCnt_temp := to_unsigned(0, 4);
                    TxD_reg_next <= '1';
                    Wr_reg_next <= '0';
                END IF;

            WHEN IN_START =>
                is_TxdPro_next <= IN_DELAY2;
                Wr_reg_next <= '0';
            WHEN IN_STOP =>

                IF RateCnt = 0 THEN 
                    is_TxdPro_next <= IN_IDLE;
                    BitCnt_temp := to_unsigned(0, 4);
                    TxD_reg_next <= '1';
                    Wr_reg_next <= '0';
                END IF;

            WHEN OTHERS => 
                is_TxdPro_next <= IN_IDLE;
                BitCnt_temp := to_unsigned(0, 4);
                TxD_reg_next <= '1';
                Wr_reg_next <= '0';
        END CASE;


        CASE is_CntPro IS
            WHEN IN_DEC =>

                IF RateCnt = 0 THEN 
                    RateCnt_next <= to_unsigned(15, 5);

                    IF BitCnt_temp = 9 THEN 
                        is_CntPro_next <= IN_Last;
                    ELSE 
                        is_CntPro_next <= IN_DEC;
                    END IF;

                ELSE 
                    RateCnt_next <= RateCnt - 1;
                END IF;

            WHEN IN_Last =>

                IF RateCnt = 0 THEN 
                    is_CntPro_next <= IN_WAIT;
                    RateCnt_next <= to_unsigned(15, 5);
                ELSE 
                    RateCnt_next <= RateCnt - 1;
                END IF;

            WHEN IN_WAIT =>

                IF TxD_reg = '0' THEN 
                    RateCnt_next <= to_unsigned(15, 5);
                    is_CntPro_next <= IN_DEC;
                ELSE 
                    is_CntPro_next <= IN_WAIT;
                    RateCnt_next <= to_unsigned(15, 5);
                END IF;

            WHEN OTHERS => 
                is_CntPro_next <= IN_WAIT;
                RateCnt_next <= to_unsigned(15, 5);
        END CASE;

        BitCnt_next <= BitCnt_temp;
    END PROCESS TxdChart;

    TxD <= TxD_reg_next;
    Wr <= Wr_reg_next;
END fsm_SFHDL;