fir5k.vhd

通带为4500到5500的带通fir的VHDL程序

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

ENTITY fir5k IS
   PORT( clk          :   IN    std_logic; 
         clkin        :   IN    std_logic; 
         rst          :   IN    std_logic;                   
         filter_in    :   IN    std_logic_vector(23 DOWNTO 0); 
         filter_out   :   OUT   std_logic_vector(23 DOWNTO 0)   
         );
END fir5k;

ARCHITECTURE rtl OF fir5k IS
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(23 DOWNTO 0);
  TYPE signed_array IS ARRAY (33 DOWNTO 0) OF signed(9 DOWNTO 0);
  CONSTANT coeff : signed_array :=
            (0 => to_signed(5, 10),
             1 => to_signed(-16, 10),
             2 => to_signed(-11, 10),
             3 => to_signed(-6, 10),
             4 => to_signed(2, 10),
             5 => to_signed(7, 10),
             6 => to_signed(6, 10),
             7 => to_signed(2, 10),
             8 => to_signed(1, 10),
             9 => to_signed(7, 10),
             10 => to_signed(14, 10),
             11 => to_signed(10, 10),
             12 => to_signed(-13, 10),
             13 => to_signed(-44, 10),
             14 => to_signed(-56, 10),
             15 => to_signed(-26, 10),
             16 => to_signed(42, 10),
             17 => to_signed(108, 10),
             18 => to_signed(117, 10),
             19 => to_signed(40, 10),
             20 => to_signed(-90, 10),
             21 => to_signed(-192, 10),
             22 => to_signed(-184, 10),
             23 => to_signed(-45, 10),
             24 => to_signed(151, 10),
             25 => to_signed(279, 10),
             26 => to_signed(239, 10),
             27 => to_signed(36, 10),
             28 => to_signed(-212, 10),
             29 => to_signed(-344, 10),
             30 => to_signed(-265, 10),
             31 => to_signed(-14, 10),
             32 => to_signed(255, 10),
             33 => to_signed(369, 10)
             );
  SIGNAL count          : integer range 34 downto 0:=0;
  SIGNAL a,b,c          : std_logic:='0';
  SIGNAL delay_pipeline : delay_pipeline_type(0 TO 66):=(OTHERS=>to_signed(0, 24));
   
  BEGIN
  c<=a xor  b;
  
  PROCESS (clk,rst)
  BEGIN
   IF rst='0' then
      a<='0';
      delay_pipeline<=(others=>to_signed(0, 24));
   ELSIF clk'event AND clk = '1' THEN
       delay_pipeline(0) <= signed(filter_in);
       delay_pipeline(1 TO 66) <= delay_pipeline(0 TO 65);
       a<=not a;
   END IF;
   END PROCESS;

  PROCESS (clkin,rst)
  VARIABLE product        : signed(34 DOWNTO 0):=to_signed(0, 35);                    
  VARIABLE add_temp       : signed(35 DOWNTO 0):=to_signed(0, 36);     
  BEGIN
    IF clkin'event AND clkin = '1' THEN
     IF rst='0' then
        b<='0';
        product :=to_signed(0, 35);                    
        add_temp:=to_signed(0, 36); 
        count<=0;
     elsIF c='1' THEN
          IF count=34 THEN
             filter_out<= std_logic_vector(resize(signed(to_stdlogicvector(to_bitvector(std_logic_vector(add_temp)) sra 12)),24));
             count<= 0;
             product:=to_signed(0, 35);
             add_temp:=to_signed(0, 36);
             b<=not b;
          elsif count=33 then
             product:=coeff(count)*(resize(delay_pipeline(count),25));
             add_temp:=add_temp+product;
             count<=count+1;             
          else
             product:=coeff(count)*(resize(delay_pipeline(count),25)+resize(delay_pipeline(66-count),25));
             add_temp:=add_temp+product;
             count<=count+1;             
         end if;
     END IF;
    end if;
 END PROCESS;  
END rtl;