dds.rpt

使用VHDL硬件描述语言实现了直接频率合成器的制作

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC29 colred1
        | +----------------------------- LC25 colred2
        | | +--------------------------- LC26 colred3
        | | | +------------------------- LC28 colred4
        | | | | +----------------------- LC30 colred5
        | | | | | +--------------------- LC19 colred12
        | | | | | | +------------------- LC20 colred13
        | | | | | | | +----------------- LC32 colred14
        | | | | | | | | +--------------- LC22 row1
        | | | | | | | | | +------------- LC21 row2
        | | | | | | | | | | +----------- LC18 row3
        | | | | | | | | | | | +--------- LC17 row4
        | | | | | | | | | | | | +------- LC23 row5
        | | | | | | | | | | | | | +----- LC31 row6
        | | | | | | | | | | | | | | +--- LC27 row7
        | | | | | | | | | | | | | | | +- LC24 row8
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> - - - * * * * * * * * * * * * * | - * | <-- inputclk0
5    -> - - - * * * * * * * * * * * * * | - * | <-- inputclk1
6    -> - - - * * * - * * * * * * * * * | - * | <-- inputclk2


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                    e:\dds\dds.rpt
dds

** EQUATIONS **

inputclk0 : INPUT;
inputclk1 : INPUT;
inputclk2 : INPUT;

-- Node name is 'colred1' 
-- Equation name is 'colred1', location is LC029, type is output.
 colred1 = LCELL( GND $  VCC);

-- Node name is 'colred2' 
-- Equation name is 'colred2', location is LC025, type is output.
 colred2 = LCELL( GND $  VCC);

-- Node name is 'colred3' 
-- Equation name is 'colred3', location is LC026, type is output.
 colred3 = LCELL( GND $  GND);

-- Node name is 'colred4' 
-- Equation name is 'colred4', location is LC028, type is output.
 colred4 = LCELL( _EQ001 $  VCC);
  _EQ001 =  inputclk0 &  inputclk1 &  inputclk2
         # !inputclk0 & !inputclk1 & !inputclk2;

-- Node name is 'colred5' 
-- Equation name is 'colred5', location is LC030, type is output.
 colred5 = LCELL( _EQ002 $  VCC);
  _EQ002 =  inputclk0 &  inputclk1 &  inputclk2
         # !inputclk0 & !inputclk1 & !inputclk2;

-- Node name is 'colred6' 
-- Equation name is 'colred6', location is LC009, type is output.
 colred6 = LCELL( GND $  GND);

-- Node name is 'colred7' 
-- Equation name is 'colred7', location is LC008, type is output.
 colred7 = LCELL( GND $  VCC);

-- Node name is 'colred8' 
-- Equation name is 'colred8', location is LC007, type is output.
 colred8 = LCELL( GND $  VCC);

-- Node name is 'colred9' 
-- Equation name is 'colred9', location is LC004, type is output.
 colred9 = LCELL( GND $  VCC);

-- Node name is 'colred10' 
-- Equation name is 'colred10', location is LC005, type is output.
 colred10 = LCELL( GND $  VCC);

-- Node name is 'colred11' 
-- Equation name is 'colred11', location is LC006, type is output.
 colred11 = LCELL( GND $  GND);

-- Node name is 'colred12' 
-- Equation name is 'colred12', location is LC019, type is output.
 colred12 = LCELL( _EQ003 $  VCC);
  _EQ003 =  inputclk0 &  inputclk1 & !inputclk2
         # !inputclk0 & !inputclk1 &  inputclk2;

-- Node name is 'colred13' 
-- Equation name is 'colred13', location is LC020, type is output.
 colred13 = LCELL(!inputclk1 $  inputclk0);

-- Node name is 'colred14' 
-- Equation name is 'colred14', location is LC032, type is output.
 colred14 = LCELL( _EQ004 $  VCC);
  _EQ004 =  inputclk0 &  inputclk1 &  inputclk2
         # !inputclk0 & !inputclk1 & !inputclk2;

-- Node name is 'colred15' 
-- Equation name is 'colred15', location is LC011, type is output.
 colred15 = LCELL( GND $  VCC);

-- Node name is 'colred16' 
-- Equation name is 'colred16', location is LC010, type is output.
 colred16 = LCELL( GND $  VCC);

-- Node name is 'row1' 
-- Equation name is 'row1', location is LC022, type is output.
 row1    = LCELL( _EQ005 $  GND);
  _EQ005 = !inputclk0 & !inputclk1 & !inputclk2;

-- Node name is 'row2' 
-- Equation name is 'row2', location is LC021, type is output.
 row2    = LCELL( _EQ006 $  GND);
  _EQ006 =  inputclk0 & !inputclk1 & !inputclk2;

-- Node name is 'row3' 
-- Equation name is 'row3', location is LC018, type is output.
 row3    = LCELL( _EQ007 $  GND);
  _EQ007 = !inputclk0 &  inputclk1 & !inputclk2;

-- Node name is 'row4' 
-- Equation name is 'row4', location is LC017, type is output.
 row4    = LCELL( _EQ008 $  GND);
  _EQ008 =  inputclk0 &  inputclk1 & !inputclk2;

-- Node name is 'row5' 
-- Equation name is 'row5', location is LC023, type is output.
 row5    = LCELL( _EQ009 $  GND);
  _EQ009 = !inputclk0 & !inputclk1 &  inputclk2;

-- Node name is 'row6' 
-- Equation name is 'row6', location is LC031, type is output.
 row6    = LCELL( _EQ010 $  GND);
  _EQ010 =  inputclk0 & !inputclk1 &  inputclk2;

-- Node name is 'row7' 
-- Equation name is 'row7', location is LC027, type is output.
 row7    = LCELL( _EQ011 $  GND);
  _EQ011 = !inputclk0 &  inputclk1 &  inputclk2;

-- Node name is 'row8' 
-- Equation name is 'row8', location is LC024, type is output.
 row8    = LCELL( _EQ012 $  GND);
  _EQ012 =  inputclk0 &  inputclk1 &  inputclk2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                             e:\dds\dds.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,358K