dds_graphic.rpt

使用VHDL硬件描述语言实现了直接频率合成器的制作

         # !_LC4_E28;

-- Node name is '|select:2|:93' from file "select.tdf" line 11, column 24
-- Equation name is '_LC7_D12', type is buried 
_LC7_D12 = LCELL( _EQ033);
  _EQ033 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:95' from file "select.tdf" line 11, column 24
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = LCELL( _EQ034);
  _EQ034 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:99' from file "select.tdf" line 11, column 24
-- Equation name is '_LC8_D12', type is buried 
_LC8_D12 = LCELL( _EQ035);
  _EQ035 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         # !_LC1_D9;

-- Node name is '|select:2|:101' from file "select.tdf" line 11, column 24
-- Equation name is '_LC4_D12', type is buried 
_LC4_D12 = LCELL( _EQ036);
  _EQ036 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         # !_LC1_D9;

-- Node name is '|select:2|:105' from file "select.tdf" line 11, column 24
-- Equation name is '_LC8_C5', type is buried 
_LC8_C5  = LCELL( _EQ037);
  _EQ037 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:107' from file "select.tdf" line 11, column 24
-- Equation name is '_LC3_C5', type is buried 
_LC3_C5  = LCELL( _EQ038);
  _EQ038 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:109' from file "select.tdf" line 11, column 24
-- Equation name is '_LC1_F36', type is buried 
_LC1_F36 = LCELL( _EQ039);
  _EQ039 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:111' from file "select.tdf" line 11, column 24
-- Equation name is '_LC7_F1', type is buried 
_LC7_F1  = LCELL( _EQ040);
  _EQ040 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:115' from file "select.tdf" line 11, column 24
-- Equation name is '_LC2_F36', type is buried 
_LC2_F36 = LCELL( _EQ041);
  _EQ041 =  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:117' from file "select.tdf" line 11, column 24
-- Equation name is '_LC1_E33', type is buried 
_LC1_E33 = LCELL( _EQ042);
  _EQ042 = !_LC2_E20
         # !_LC2_E33
         #  _LC7_E33
         # !_LC1_D9;

-- Node name is '|select:2|:119' from file "select.tdf" line 11, column 24
-- Equation name is '_LC6_D12', type is buried 
_LC6_D12 = LCELL( _EQ043);
  _EQ043 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         # !_LC1_D9;

-- Node name is '|select:2|:121' from file "select.tdf" line 11, column 24
-- Equation name is '_LC2_C7', type is buried 
_LC2_C7  = LCELL( _EQ044);
  _EQ044 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:123' from file "select.tdf" line 11, column 24
-- Equation name is '_LC4_F1', type is buried 
_LC4_F1  = LCELL( _EQ045);
  _EQ045 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         # !_LC1_D9;

-- Node name is '|select:2|:126' from file "select.tdf" line 12, column 20
-- Equation name is '_LC3_D12', type is buried 
_LC3_D12 = LCELL( _EQ046);
  _EQ046 =  _LC6_E33
         # !_LC5_E23
         # !_LC4_E28
         #  _LC1_D9;

-- Node name is '|select:2|:129' from file "select.tdf" line 12, column 20
-- Equation name is '_LC8_F1', type is buried 
_LC8_F1  = LCELL( _EQ047);
  _EQ047 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:135' from file "select.tdf" line 12, column 20
-- Equation name is '_LC4_E33', type is buried 
_LC4_E33 = LCELL( _EQ048);
  _EQ048 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         #  _LC1_D9;

-- Node name is '|select:2|:138' from file "select.tdf" line 12, column 20
-- Equation name is '_LC8_E33', type is buried 
_LC8_E33 = LCELL( _EQ049);
  _EQ049 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         #  _LC1_D9;

-- Node name is '|select:2|:144' from file "select.tdf" line 12, column 20
-- Equation name is '_LC1_F1', type is buried 
_LC1_F1  = LCELL( _EQ050);
  _EQ050 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:147' from file "select.tdf" line 12, column 20
-- Equation name is '_LC5_D12', type is buried 
_LC5_D12 = LCELL( _EQ051);
  _EQ051 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:150' from file "select.tdf" line 12, column 20
-- Equation name is '_LC5_F1', type is buried 
_LC5_F1  = LCELL( _EQ052);
  _EQ052 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:153' from file "select.tdf" line 12, column 20
-- Equation name is '_LC3_F1', type is buried 
_LC3_F1  = LCELL( _EQ053);
  _EQ053 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:159' from file "select.tdf" line 12, column 20
-- Equation name is '_LC2_F1', type is buried 
_LC2_F1  = LCELL( _EQ054);
  _EQ054 =  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:162' from file "select.tdf" line 12, column 20
-- Equation name is '_LC5_E33', type is buried 
_LC5_E33 = LCELL( _EQ055);
  _EQ055 =  _LC7_E33
         # !_LC2_E20
         # !_LC2_E33
         #  _LC1_D9;

-- Node name is '|select:2|:165' from file "select.tdf" line 12, column 20
-- Equation name is '_LC2_C5', type is buried 
_LC2_C5  = LCELL( _EQ056);
  _EQ056 =  _LC2_D12 & !_LC3_E33
         #  _LC1_D12 & !_LC3_E33
         # !_LC2_D12 &  _LC3_E33
         # !_LC1_D12 &  _LC3_E33
         #  _LC1_D9;

-- Node name is '|select:2|:168' from file "select.tdf" line 12, column 20
-- Equation name is '_LC6_F1', type is buried 
_LC6_F1  = LCELL( _EQ057);
  _EQ057 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;

-- Node name is '|select:2|:171' from file "select.tdf" line 12, column 20
-- Equation name is '_LC8_F36', type is buried 
_LC8_F36 = LCELL( _EQ058);
  _EQ058 = !_LC5_E23
         # !_LC4_E28
         #  _LC6_E33
         #  _LC1_D9;



Project Information                                     e:\dds\dds_graphic.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,997K