📄 dds_graphic.rpt
字号:
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
88 - - D -- OUTPUT 0 1 0 0 green1
114 - - - 06 OUTPUT 0 1 0 0 green2
98 - - B -- OUTPUT 0 1 0 0 green3
90 - - D -- OUTPUT 0 1 0 0 green4
87 - - E -- OUTPUT 0 1 0 0 green5
89 - - D -- OUTPUT 0 1 0 0 green6
95 - - C -- OUTPUT 0 1 0 0 green7
99 - - B -- OUTPUT 0 1 0 0 green8
36 - - - 36 OUTPUT 0 1 0 0 green9
33 - - F -- OUTPUT 0 1 0 0 green10
29 - - E -- OUTPUT 0 1 0 0 green11
31 - - F -- OUTPUT 0 1 0 0 green12
30 - - F -- OUTPUT 0 1 0 0 green13
63 - - - 11 OUTPUT 0 1 0 0 green14
68 - - - 07 OUTPUT 0 1 0 0 green15
73 - - - 01 OUTPUT 0 1 0 0 green16
80 - - F -- OUTPUT 0 1 0 0 red1
100 - - A -- OUTPUT 0 1 0 0 red2
102 - - A -- OUTPUT 0 1 0 0 red3
96 - - C -- OUTPUT 0 1 0 0 red4
83 - - E -- OUTPUT 0 1 0 0 red5
91 - - D -- OUTPUT 0 1 0 0 red6
97 - - C -- OUTPUT 0 1 0 0 red7
101 - - A -- OUTPUT 0 1 0 0 red8
32 - - F -- OUTPUT 0 1 0 0 red9
27 - - E -- OUTPUT 0 1 0 0 red10
65 - - - 09 OUTPUT 0 1 0 0 red11
81 - - F -- OUTPUT 0 1 0 0 red12
28 - - E -- OUTPUT 0 1 0 0 red13
70 - - - 05 OUTPUT 0 1 0 0 red14
79 - - F -- OUTPUT 0 1 0 0 red15
78 - - F -- OUTPUT 0 1 0 0 red16
51 - - - 20 OUTPUT 0 1 0 0 row1
59 - - - 16 OUTPUT 0 1 0 0 row2
60 - - - 15 OUTPUT 0 1 0 0 row3
48 - - - 24 OUTPUT 0 1 0 0 row4
46 - - - 27 OUTPUT 0 1 0 0 row5
43 - - - 30 OUTPUT 0 1 0 0 row6
41 - - - 31 OUTPUT 0 1 0 0 row7
38 - - - 34 OUTPUT 0 1 0 0 row8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - D 14 DFFE + 0 1 0 3 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QH (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:1)
- 8 - D 06 DFFE + 0 3 0 1 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QG (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:2)
- 7 - D 06 DFFE + 0 2 0 2 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QF (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:3)
- 6 - D 06 DFFE + 0 1 0 3 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QE (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:4)
- 4 - D 06 DFFE + 0 3 0 1 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QD (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:5)
- 3 - D 06 DFFE + 0 2 0 2 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 1 - D 06 DFFE + 0 1 0 3 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 2 - D 02 DFFE + 0 0 0 4 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 5 - D 06 AND2 0 4 0 4 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:291
- 2 - D 06 AND2 0 4 0 4 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c0|:297
- 3 - D 09 DFFE +s 0 3 1 0 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE~1 (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|~4~1)
- 5 - D 09 DFFE +s 0 3 1 0 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE~2 (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|~4~2)
- 7 - D 09 DFFE +s 0 3 1 0 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE~3 (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|~4~3)
- 6 - D 04 DFFE +s 0 3 1 0 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE~4 (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|~4~4)
- 6 - D 09 DFFE +s 0 3 1 0 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE~5 (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|~4~5)
- 1 - D 09 DFFE + 0 3 1 26 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QE (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:4)
- 2 - D 09 DFFE + 0 2 0 6 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QD (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:5)
- 4 - D 09 DFFE + 0 1 0 7 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QC (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:6)
- 3 - D 14 DFFE + 0 3 0 1 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QB (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:7)
- 2 - D 14 DFFE + 0 2 0 2 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|QA (|counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:8)
- 6 - D 14 AND2 0 4 0 8 |counter2:8|lpm_counter:lpm_counter_component|f8count:p8c1|:287
- 3 - E 33 DFFE + 0 2 0 15 |count:6|lpm_counter:lpm_counter_component|f8count:p8c0|QC (|count:6|lpm_counter:lpm_counter_component|f8count:p8c0|:6)
- 2 - D 12 DFFE + 0 1 0 16 |count:6|lpm_counter:lpm_counter_component|f8count:p8c0|QB (|count:6|lpm_counter:lpm_counter_component|f8count:p8c0|:7)
- 1 - D 12 DFFE + 0 0 0 17 |count:6|lpm_counter:lpm_counter_component|f8count:p8c0|QA (|count:6|lpm_counter:lpm_counter_component|f8count:p8c0|:8)
- 2 - E 20 AND2 ! 0 3 1 2 |dds:1|:55
- 2 - C 16 AND2 ! 0 3 1 0 |dds:1|:69
- 4 - C 16 AND2 ! 0 3 1 0 |dds:1|:94
- 5 - E 23 AND2 ! 0 3 1 17 |dds:1|:123
- 4 - E 28 AND2 ! 0 3 1 17 |dds:1|:151
- 1 - E 30 AND2 ! 0 3 1 0 |dds:1|:180
- 2 - E 31 AND2 ! 0 3 1 0 |dds:1|:209
- 2 - E 33 AND2 ! 0 3 1 2 |dds:1|:239
- 6 - E 33 OR2 0 3 0 18 |dds:1|:254
- 7 - E 33 OR2 s 0 2 0 2 |dds:1|~256~1
- 7 - D 12 OR2 0 4 1 0 |select:2|:93
- 1 - C 05 OR2 0 4 1 0 |select:2|:95
- 8 - D 12 OR2 0 4 1 0 |select:2|:99
- 4 - D 12 OR2 0 4 1 0 |select:2|:101
- 8 - C 05 OR2 0 4 1 0 |select:2|:105
- 3 - C 05 OR2 0 4 1 0 |select:2|:107
- 1 - F 36 OR2 0 4 1 0 |select:2|:109
- 7 - F 01 OR2 0 4 1 0 |select:2|:111
- 2 - F 36 OR2 0 2 1 0 |select:2|:115
- 1 - E 33 OR2 0 4 1 0 |select:2|:117
- 6 - D 12 OR2 0 4 1 0 |select:2|:119
- 2 - C 07 OR2 0 4 1 0 |select:2|:121
- 4 - F 01 OR2 0 4 1 0 |select:2|:123
- 3 - D 12 OR2 0 4 1 0 |select:2|:126
- 8 - F 01 OR2 0 4 1 0 |select:2|:129
- 4 - E 33 OR2 0 4 1 0 |select:2|:135
- 8 - E 33 OR2 0 4 1 0 |select:2|:138
- 1 - F 01 OR2 0 4 1 0 |select:2|:144
- 5 - D 12 OR2 0 4 1 0 |select:2|:147
- 5 - F 01 OR2 0 4 1 0 |select:2|:150
- 3 - F 01 OR2 0 4 1 0 |select:2|:153
- 2 - F 01 OR2 0 2 1 0 |select:2|:159
- 5 - E 33 OR2 0 4 1 0 |select:2|:162
- 2 - C 05 OR2 0 4 1 0 |select:2|:165
- 6 - F 01 OR2 0 4 1 0 |select:2|:168
- 8 - F 36 OR2 0 4 1 0 |select:2|:171
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 5/144( 3%) 5/ 72( 6%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 11/144( 7%) 4/ 72( 5%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
E: 8/144( 5%) 1/ 72( 1%) 3/ 72( 4%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
F: 7/144( 4%) 3/ 72( 4%) 2/ 72( 2%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 21 clk
Device-Specific Information: e:\dds\dds_graphic.rpt
dds_graphic
** EQUATIONS **
clk : INPUT;
-- Node name is 'green1'
-- Equation name is 'green1', type is output
green1 = _LC7_D12;
-- Node name is 'green2'
-- Equation name is 'green2', type is output
green2 = _LC1_C5;
-- Node name is 'green3'
-- Equation name is 'green3', type is output
green3 = !_LC6_D4;
-- Node name is 'green4'
-- Equation name is 'green4', type is output
green4 = _LC8_D12;
-- Node name is 'green5'
-- Equation name is 'green5', type is output
green5 = _LC4_D12;
-- Node name is 'green6'
-- Equation name is 'green6', type is output
green6 = !_LC6_D9;
-- Node name is 'green7'
-- Equation name is 'green7', type is output
green7 = _LC8_C5;
-- Node name is 'green8'
-- Equation name is 'green8', type is output
green8 = _LC3_C5;
-- Node name is 'green9'
-- Equation name is 'green9', type is output
green9 = _LC1_F36;
-- Node name is 'green10'
-- Equation name is 'green10', type is output
green10 = _LC7_F1;
-- Node name is 'green11'
-- Equation name is 'green11', type is output
green11 = !_LC7_D9;
-- Node name is 'green12'
-- Equation name is 'green12', type is output
green12 = _LC2_F36;
-- Node name is 'green13'
-- Equation name is 'green13', type is output
green13 = _LC1_E33;
-- Node name is 'green14'
-- Equation name is 'green14', type is output
green14 = _LC6_D12;
-- Node name is 'green15'
-- Equation name is 'green15', type is output
green15 = _LC2_C7;
-- Node name is 'green16'
-- Equation name is 'green16', type is output
green16 = _LC4_F1;
-- Node name is 'red1'
-- Equation name is 'red1', type is output
red1 = _LC3_D12;
-- Node name is 'red2'
-- Equation name is 'red2', type is output
red2 = _LC8_F1;
-- Node name is 'red3'
-- Equation name is 'red3', type is output
red3 = _LC1_D9;
-- Node name is 'red4'
-- Equation name is 'red4', type is output
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -