select.rpt

使用VHDL硬件描述语言实现了直接频率合成器的制作

Logic Array Block 'D':

                                 Logic cells placed in LAB 'D'
        +----------------------- LC53 DATAOUT01
        | +--------------------- LC62 DATAOUT02
        | | +------------------- LC61 DATAOUT03
        | | | +----------------- LC60 DATAOUT04
        | | | | +--------------- LC59 DATAOUT05
        | | | | | +------------- LC57 DATAOUT06
        | | | | | | +----------- LC54 DATAOUT11
        | | | | | | | +--------- LC56 DATAOUT12
        | | | | | | | | +------- LC64 DATAOUT13
        | | | | | | | | | +----- LC52 DATAOUT14
        | | | | | | | | | | +--- LC49 DATAOUT15
        | | | | | | | | | | | +- LC51 DATAOUT16
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':

Pin
17   -> * - - - - - * - - - - - | - - - * | <-- DATA1
15   -> - * - - - - - * - - - - | - - - * | <-- DATA2
14   -> - - * - - - - - * - - - | - - - * | <-- DATA3
13   -> - - - * - - - - - * - - | - - - * | <-- DATA4
12   -> - - - - * - - - - - * - | - - - * | <-- DATA5
10   -> - - - - - * - - - - - * | - - - * | <-- DATA6
67   -> - - - - - - - - - - - - | - * - - | <-- DATA14
18   -> * * * * * * * * * * * * | - * * * | <-- SEL


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 e:\dds\select.rpt
select

** EQUATIONS **

DATA1    : INPUT;
DATA2    : INPUT;
DATA3    : INPUT;
DATA4    : INPUT;
DATA5    : INPUT;
DATA6    : INPUT;
DATA7    : INPUT;
DATA8    : INPUT;
DATA9    : INPUT;
DATA10   : INPUT;
DATA11   : INPUT;
DATA12   : INPUT;
DATA13   : INPUT;
DATA14   : INPUT;
DATA15   : INPUT;
DATA16   : INPUT;
SEL      : INPUT;

-- Node name is 'DATAOUT01' 
-- Equation name is 'DATAOUT01', location is LC053, type is output.
 DATAOUT01 = LCELL( _EQ001 $  DATA1);
  _EQ001 = !DATA1 &  SEL;

-- Node name is 'DATAOUT02' 
-- Equation name is 'DATAOUT02', location is LC062, type is output.
 DATAOUT02 = LCELL( _EQ002 $  DATA2);
  _EQ002 = !DATA2 &  SEL;

-- Node name is 'DATAOUT03' 
-- Equation name is 'DATAOUT03', location is LC061, type is output.
 DATAOUT03 = LCELL( _EQ003 $  DATA3);
  _EQ003 = !DATA3 &  SEL;

-- Node name is 'DATAOUT04' 
-- Equation name is 'DATAOUT04', location is LC060, type is output.
 DATAOUT04 = LCELL( _EQ004 $  DATA4);
  _EQ004 = !DATA4 &  SEL;

-- Node name is 'DATAOUT05' 
-- Equation name is 'DATAOUT05', location is LC059, type is output.
 DATAOUT05 = LCELL( _EQ005 $  DATA5);
  _EQ005 = !DATA5 &  SEL;

-- Node name is 'DATAOUT06' 
-- Equation name is 'DATAOUT06', location is LC057, type is output.
 DATAOUT06 = LCELL( _EQ006 $  DATA6);
  _EQ006 = !DATA6 &  SEL;

-- Node name is 'DATAOUT07' 
-- Equation name is 'DATAOUT07', location is LC048, type is output.
 DATAOUT07 = LCELL( _EQ007 $  DATA7);
  _EQ007 = !DATA7 &  SEL;

-- Node name is 'DATAOUT08' 
-- Equation name is 'DATAOUT08', location is LC046, type is output.
 DATAOUT08 = LCELL( _EQ008 $  DATA8);
  _EQ008 = !DATA8 &  SEL;

-- Node name is 'DATAOUT09' 
-- Equation name is 'DATAOUT09', location is LC045, type is output.
 DATAOUT09 = LCELL( _EQ009 $  DATA9);
  _EQ009 = !DATA9 &  SEL;

-- Node name is 'DATAOUT010' 
-- Equation name is 'DATAOUT010', location is LC044, type is output.
 DATAOUT010 = LCELL( _EQ010 $  DATA10);
  _EQ010 = !DATA10 &  SEL;

-- Node name is 'DATAOUT011' 
-- Equation name is 'DATAOUT011', location is LC043, type is output.
 DATAOUT011 = LCELL( _EQ011 $  DATA11);
  _EQ011 = !DATA11 &  SEL;

-- Node name is 'DATAOUT11' 
-- Equation name is 'DATAOUT11', location is LC054, type is output.
 DATAOUT11 = LCELL( _EQ012 $  VCC);
  _EQ012 = !DATA1 &  SEL;

-- Node name is 'DATAOUT012' 
-- Equation name is 'DATAOUT012', location is LC041, type is output.
 DATAOUT012 = LCELL( _EQ013 $  DATA12);
  _EQ013 = !DATA12 &  SEL;

-- Node name is 'DATAOUT12' 
-- Equation name is 'DATAOUT12', location is LC056, type is output.
 DATAOUT12 = LCELL( _EQ014 $  VCC);
  _EQ014 = !DATA2 &  SEL;

-- Node name is 'DATAOUT013' 
-- Equation name is 'DATAOUT013', location is LC019, type is output.
 DATAOUT013 = LCELL( _EQ015 $  DATA13);
  _EQ015 = !DATA13 &  SEL;

-- Node name is 'DATAOUT13' 
-- Equation name is 'DATAOUT13', location is LC064, type is output.
 DATAOUT13 = LCELL( _EQ016 $  VCC);
  _EQ016 = !DATA3 &  SEL;

-- Node name is 'DATAOUT014' 
-- Equation name is 'DATAOUT014', location is LC032, type is output.
 DATAOUT014 = LCELL( _EQ017 $  DATA14);
  _EQ017 = !DATA14 &  SEL;

-- Node name is 'DATAOUT14' 
-- Equation name is 'DATAOUT14', location is LC052, type is output.
 DATAOUT14 = LCELL( _EQ018 $  VCC);
  _EQ018 = !DATA4 &  SEL;

-- Node name is 'DATAOUT015' 
-- Equation name is 'DATAOUT015', location is LC017, type is output.
 DATAOUT015 = LCELL( _EQ019 $  DATA15);
  _EQ019 = !DATA15 &  SEL;

-- Node name is 'DATAOUT15' 
-- Equation name is 'DATAOUT15', location is LC049, type is output.
 DATAOUT15 = LCELL( _EQ020 $  VCC);
  _EQ020 = !DATA5 &  SEL;

-- Node name is 'DATAOUT016' 
-- Equation name is 'DATAOUT016', location is LC025, type is output.
 DATAOUT016 = LCELL( _EQ021 $  DATA16);
  _EQ021 = !DATA16 &  SEL;

-- Node name is 'DATAOUT16' 
-- Equation name is 'DATAOUT16', location is LC051, type is output.
 DATAOUT16 = LCELL( _EQ022 $  VCC);
  _EQ022 = !DATA6 &  SEL;

-- Node name is 'DATAOUT17' 
-- Equation name is 'DATAOUT17', location is LC033, type is output.
 DATAOUT17 = LCELL( _EQ023 $  VCC);
  _EQ023 = !DATA7 &  SEL;

-- Node name is 'DATAOUT18' 
-- Equation name is 'DATAOUT18', location is LC035, type is output.
 DATAOUT18 = LCELL( _EQ024 $  VCC);
  _EQ024 = !DATA8 &  SEL;

-- Node name is 'DATAOUT19' 
-- Equation name is 'DATAOUT19', location is LC036, type is output.
 DATAOUT19 = LCELL( _EQ025 $  VCC);
  _EQ025 = !DATA9 &  SEL;

-- Node name is 'DATAOUT110' 
-- Equation name is 'DATAOUT110', location is LC037, type is output.
 DATAOUT110 = LCELL( _EQ026 $  VCC);
  _EQ026 = !DATA10 &  SEL;

-- Node name is 'DATAOUT111' 
-- Equation name is 'DATAOUT111', location is LC038, type is output.
 DATAOUT111 = LCELL( _EQ027 $  VCC);
  _EQ027 = !DATA11 &  SEL;

-- Node name is 'DATAOUT112' 
-- Equation name is 'DATAOUT112', location is LC040, type is output.
 DATAOUT112 = LCELL( _EQ028 $  VCC);
  _EQ028 = !DATA12 &  SEL;

-- Node name is 'DATAOUT113' 
-- Equation name is 'DATAOUT113', location is LC027, type is output.
 DATAOUT113 = LCELL( _EQ029 $  VCC);
  _EQ029 = !DATA13 &  SEL;

-- Node name is 'DATAOUT114' 
-- Equation name is 'DATAOUT114', location is LC028, type is output.
 DATAOUT114 = LCELL( _EQ030 $  VCC);
  _EQ030 = !DATA14 &  SEL;

-- Node name is 'DATAOUT115' 
-- Equation name is 'DATAOUT115', location is LC029, type is output.
 DATAOUT115 = LCELL( _EQ031 $  VCC);
  _EQ031 = !DATA15 &  SEL;

-- Node name is 'DATAOUT116' 
-- Equation name is 'DATAOUT116', location is LC030, type is output.
 DATAOUT116 = LCELL( _EQ032 $  VCC);
  _EQ032 = !DATA16 &  SEL;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          e:\dds\select.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,969K