vgasignal.v

一个是用Verilog的程序 还可以用

module VGAsignal
  (
	CLK,
	MD,
	HS,
	VS,
	R,
	G,
	B
  );
  	input CLK;
  	input MD;  //选择色条
	output HS;  //水平扫描信号
	output VS;  //垂直扫描信号
	output R,G,B;  //三颜色信号
	
	reg HS1,VS1;
	reg [1:0] MMD;
	reg [5:0] FS;
	reg [4:0] CC;
	reg [8:0] LL;
	reg [3:1] GRBX, GRBY, GRBP;
    
	wire [3:1] GRB;
	wire FCLK, CCLK;
	
	assign GRB[1] = (GRBP[1] ^ MD) & HS1 & VS1;
	assign GRB[2] = (GRBP[2] ^ MD) & HS1 & VS1;
	assign GRB[3] = (GRBP[3] ^ MD) & HS1 & VS1;
	
	always @ (posedge MD)
	begin
	  if (MD) begin
	     if (MMD == 2'b10) MMD <= 2'b00;
		 else MMD <= MMD + 1;
	  end
	end
	
	always @ (MMD)
	begin
	  	if (MMD == 2'b00) GRBP <= GRBX;
		else if (MMD == 2'b01) GRBP <= GRBY;
		else if (MMD == 2'b10) GRBP <= (GRBX ^ GRBY);
		else GRBP <= 3'b000;
	end
	
	always @ (posedge CLK)
	begin
		if (CLK) begin
			if (FS == 6'd50) FS <= 6'b00_0000;
			else FS <= FS + 1;
		end
	end
	
	assign FCLK = FS[5];  // FCLK 为 CLK 的 32 分频
	
	always @ (posedge FCLK)
	begin
		if (FCLK) begin
			if (CC == 5'd29) CC <= 5'b0_0000;
			else CC <= CC + 1;
		end
	end
	
	assign CCLK = CC[4]; // CCLK 为 FCLK 的 16 分频
	
	always @ (negedge CCLK)
	begin
		if (!CCLK) begin
			if (LL == 9'd481) LL <= 9'b0_0000_0000;
			else LL <= LL + 1;
		end
	end
	
	always @ (CC or LL)
	begin
		if (CC > 5'd23) HS1 <= 1'b0;
		else HS1 = 1'b1;
		if (LL > 9'd479) VS1 <= 1'b0;
		else VS1 = 1'b1;
	end
	
	always @ (CC or LL)
	begin
		if (CC < 5'd3)       GRBX <= 3'b111;
		else if (CC < 5'd6)  GRBX <= 3'b110;
		else if (CC < 5'd9)  GRBX <= 3'b101;
		else if (CC < 5'd12) GRBX <= 3'b100;
		else if (CC < 5'd15) GRBX <= 3'b011;
		else if (CC < 5'd18) GRBX <= 3'b010;
		else if (CC < 5'd21) GRBX <= 3'b001;
		else                 GRBX <= 3'b000;
				
		if (LL < 9'd60)       GRBY <= 3'b111;
		else if (LL < 9'd120) GRBY <= 3'b110;
		else if (LL < 9'd180) GRBY <= 3'b101;
		else if (LL < 9'd240) GRBY <= 3'b100;
		else if (LL < 9'd300) GRBY <= 3'b011;
		else if (LL < 9'd360) GRBY <= 3'b010;
		else if (LL < 9'd420) GRBY <= 3'b001;
		else                  GRBY <= 3'b000;
	end
	
	assign HS = HS1;
	assign VS = VS1;
	assign R  = GRB[2];
	assign G  = GRB[3];
	assign B  = GRB[1];
	
	endmodule