vga.map.rpt

一个是用Verilog的程序 还可以用

; VGA.bdf                          ; yes             ; User Block Diagram/Schematic File  ; D:/Verilog_VGA/VGA.bdf       ;
; VGAsignal.v                      ; yes             ; User Verilog HDL File              ; D:/Verilog_VGA/VGAsignal.v   ;
+----------------------------------+-----------------+------------------------------------+------------------------------+


+---------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                         ;
+---------------------------------------------+-----------------------+
; Resource                                    ; Usage                 ;
+---------------------------------------------+-----------------------+
; Total logic elements                        ; 70                    ;
;     -- Combinational with no register       ; 48                    ;
;     -- Register only                        ; 7                     ;
;     -- Combinational with a register        ; 15                    ;
;                                             ;                       ;
; Logic element usage by number of LUT inputs ;                       ;
;     -- 4 input functions                    ; 30                    ;
;     -- 3 input functions                    ; 4                     ;
;     -- 2 input functions                    ; 26                    ;
;     -- 1 input functions                    ; 3                     ;
;     -- 0 input functions                    ; 0                     ;
;         -- Combinational cells for routing  ; 0                     ;
;                                             ;                       ;
; Logic elements by mode                      ;                       ;
;     -- normal mode                          ; 53                    ;
;     -- arithmetic mode                      ; 17                    ;
;     -- qfbk mode                            ; 0                     ;
;     -- register cascade mode                ; 0                     ;
;     -- synchronous clear/load mode          ; 0                     ;
;     -- asynchronous clear/load mode         ; 0                     ;
;                                             ;                       ;
; Total registers                             ; 22                    ;
; Total logic cells in carry chains           ; 20                    ;
; I/O pins                                    ; 7                     ;
; Maximum fan-out node                        ; VGAsignal:inst1|CC[4] ;
; Maximum fan-out                             ; 15                    ;
; Total fan-out                               ; 221                   ;
; Average fan-out                             ; 2.87                  ;
+---------------------------------------------+-----------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name  ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; |VGA                       ; 70 (0)      ; 22           ; 0          ; 7    ; 0            ; 48 (0)       ; 7 (0)             ; 15 (0)           ; 20 (0)          ; 0 (0)      ; |VGA                 ;
;    |VGAsignal:inst1|       ; 70 (70)     ; 22           ; 0          ; 0    ; 0            ; 48 (48)      ; 7 (7)             ; 15 (15)          ; 20 (20)         ; 0 (0)      ; |VGA|VGAsignal:inst1 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |VGA|VGAsignal:inst1|GRBP[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Verilog_VGA/VGA.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sun Nov 19 23:31:52 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA
Info: Found 1 design units, including 1 entities, in source file VGA.bdf
    Info: Found entity 1: VGA
Warning (10268): Verilog HDL information at VGAsignal.v(75): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file VGAsignal.v
    Info: Found entity 1: VGAsignal
Info: Elaborating entity "VGA" for the top level hierarchy
Info: Elaborating entity "VGAsignal" for hierarchy "VGAsignal:inst1"
Warning (10230): Verilog HDL assignment warning at VGAsignal.v(35): truncated value with size 32 to match size of target (2)
Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(41): variable "GRBX" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(42): variable "GRBY" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(43): variable "GRBX" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at VGAsignal.v(43): variable "GRBY" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at VGAsignal.v(51): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at VGAsignal.v(61): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at VGAsignal.v(71): truncated value with size 32 to match size of target (9)
Info: Implemented 77 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 70 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Sun Nov 19 23:32:01 2006
    Info: Elapsed time: 00:00:10