📄 digital_clk.map.qmsg
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{ "Info" "IOPT_INFERENCING_SUMMARY" "5 " "Info: Inferred 5 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "hhtemp\[0\]~10 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: hhtemp\[0\]~10" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "hhtemp\[0\]~10" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "i109~0 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: i109~0" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "i109~0" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "i75~0 14 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=14) from the following logic: i75~0" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "i75~0" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "mmtemp\[0\]~12 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: mmtemp\[0\]~12" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "mmtemp\[0\]~12" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "count\[0\]~4 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: count\[0\]~4" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "count\[0\]~4" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" { } { { "c:/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" { } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "alt_counter_f10ke" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" { } { { "c:/quartus/libraries/megafunctions/lpm_divide.tdf" "lpm_divide" "" { Text "c:/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/sign_div_unsign.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/sign_div_unsign.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign " "Info: Found entity 1: sign_div_unsign" { } { { "c:/quartus/libraries/megafunctions/sign_div_unsign.tdf" "sign_div_unsign" "" { Text "c:/quartus/libraries/megafunctions/sign_div_unsign.tdf" 85 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/alt_u_div.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/alt_u_div.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div " "Info: Found entity 1: alt_u_div" { } { { "c:/quartus/libraries/megafunctions/alt_u_div.tdf" "alt_u_div" "" { Text "c:/quartus/libraries/megafunctions/alt_u_div.tdf" 93 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" { } { { "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "c:/quartus/libraries/megafunctions/lpm_add_sub.tdf" 103 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" { } { { "c:/quartus/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "c:/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } } } 0} } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" { } { { "c:/quartus/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/quartus/libraries/megafunctions/altshift.tdf" 34 1 0 } } } 0} } { } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "2 " "Info: Ignored 2 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "2 " "Info: Ignored 2 SOFT buffer(s)" { } { } 0} } { } 0}
{ "Warning" "WFTM_IGNORED_UNIMPLEMENTABLE_CARRY" "5 " "Warning: Ignored 5 CARRY_SUM primitives" { { "Warning" "WFTM_CARRY_MERGE_FANIN_HDR" "1 " "Warning: Ignored 1 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANIN" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] " "Warning: Can't place logic feeding CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] in single logic cell" { { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 of type CARRY_SUM" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] of type CARRY_SUM" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT_HDR" "4 " "Warning: Ignored 4 CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~19 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~19 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~20 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~20 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~12 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~12 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 of type LUT" { } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} } { } 0} } { } 0}
{ "Info" "IFTM_WANNA_REM_USR_DUPE" "" "Info: Found the following redundant logic cells in design" { { "Info" "IFTM_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41 " "Info: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41" { } { } 0} { "Info" "IFTM_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40 " "Info: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40" { } { } 0} } { } 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40 " "Info: Logic cell lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40" { } { } 0} { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41 " "Info: Logic cell lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41" { } { } 0} } { } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "293 " "Info: Implemented 293 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" { } { } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" { } { } 0} { "Info" "ISCL_SCL_TM_LCELLS" "271 " "Info: Implemented 271 logic cells" { } { } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 14:33:03 2008 " "Info: Processing ended: Tue Dec 02 14:33:03 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" { } { } 0} } { } 0}
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