📄 digital_clk.csf.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 14:33:16 2008 " "Info: Processing started: Tue Dec 02 14:33:16 2008" { } { } 0} } { } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off digital_clk -c digital_clk " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off digital_clk -c digital_clk" { } { } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "blink\[2\]~32 " "Info: Node blink\[2\]~32" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "blink\[2\]~331 " "Info: Node blink\[2\]~331" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0} } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "blink\[0\]~31 " "Info: Node blink\[0\]~31" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "blink\[0\]~329 " "Info: Node blink\[0\]~329" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0} } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 23 -1 0 } } } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "mode " "Info: Assuming node mode is an undefined clock" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 10 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } } } 0} } { } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "clk1hz " "Info: Detected ripple clock clk1hz as buffer" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1hz" } } } } } 0} { "Info" "ITDB_RIPPLE_CLK" "clk1khz " "Info: Detected ripple clock clk1khz as buffer" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1khz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sec\[4\] register min\[4\] 55.25 MHz 18.1 ns Internal " "Info: Clock clk has Internal fmax of 55.25 MHz between source register sec\[4\] and destination register min\[4\] (period= 18.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.900 ns + Longest register register " "Info: + Longest register to register delay is 15.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sec\[4\] 1 REG LC7_A22 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A22; Fanout = 4; REG Node = 'sec\[4\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { sec[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 3.300 ns i~8246 2 COMB LC3_A21 2 " "Info: 2: + IC(1.900 ns) + CELL(1.400 ns) = 3.300 ns; Loc. = LC3_A21; Fanout = 2; COMB Node = 'i~8246'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.300 ns" { sec[4] i~8246 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 5.800 ns i~13 3 COMB LC1_A21 3 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 5.800 ns; Loc. = LC1_A21; Fanout = 3; COMB Node = 'i~13'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { i~8246 i~13 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 9.100 ns i~8265 4 COMB LC3_A19 8 " "Info: 4: + IC(1.900 ns) + CELL(1.400 ns) = 9.100 ns; Loc. = LC3_A19; Fanout = 8; COMB Node = 'i~8265'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.300 ns" { i~13 i~8265 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.900 ns) 12.700 ns i~8271 5 COMB LC7_A18 1 " "Info: 5: + IC(1.700 ns) + CELL(1.900 ns) = 12.700 ns; Loc. = LC7_A18; Fanout = 1; COMB Node = 'i~8271'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.600 ns" { i~8265 i~8271 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 15.900 ns min\[4\] 6 REG LC3_A13 6 " "Info: 6: + IC(1.800 ns) + CELL(1.400 ns) = 15.900 ns; Loc. = LC3_A13; Fanout = 6; REG Node = 'min\[4\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.200 ns" { i~8271 min[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 50.31 % " "Info: Total cell delay = 8.000 ns ( 50.31 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns 49.69 % " "Info: Total interconnect delay = 7.900 ns ( 49.69 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "15.900 ns" { sec[4] i~8246 i~13 i~8265 i~8271 min[4] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns min\[4\] 4 REG LC3_A13 6 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC3_A13; Fanout = 6; REG Node = 'min\[4\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz min[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz min[4] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.500 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns sec\[4\] 4 REG LC7_A22 4 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC7_A22; Fanout = 4; REG Node = 'sec\[4\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz sec[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz sec[4] } "NODE_NAME" } } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz min[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz sec[4] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "15.900 ns" { sec[4] i~8246 i~13 i~8265 i~8271 min[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz min[4] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz sec[4] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register state\[0\] state\[2\] 125.0 MHz Internal " "Info: Clock mode Internal fmax is restricted to 125.0 MHz between source register state\[0\] and destination register state\[2\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register register " "Info: + Longest register to register delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\] 1 REG LC5_A9 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A9; Fanout = 29; REG Node = 'state\[0\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { state[0] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 1.500 ns state\[2\] 2 REG LC3_A9 38 " "Info: 2: + IC(0.600 ns) + CELL(0.900 ns) = 1.500 ns; Loc. = LC3_A9; Fanout = 38; REG Node = 'state\[2\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "1.500 ns" { state[0] state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 60.00 % " "Info: Total cell delay = 0.900 ns ( 60.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 40.00 % " "Info: Total interconnect delay = 0.600 ns ( 40.00 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "1.500 ns" { state[0] state[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock mode to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns mode 1 CLK Pin_44 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 3; CLK Node = 'mode'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { mode } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns state\[2\] 2 REG LC3_A9 38 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_A9; Fanout = 38; REG Node = 'state\[2\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { mode state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 3.900 ns - Longest register " "Info: - Longest clock path from clock mode to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns mode 1 CLK Pin_44 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_44; Fanout = 3; CLK Node = 'mode'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { mode } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns state\[0\] 2 REG LC5_A9 29 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_A9; Fanout = 29; REG Node = 'state\[0\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { mode state[0] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[0] } "NODE_NAME" } } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "1.500 ns" { state[0] state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "3.900 ns" { mode state[0] } "NODE_NAME" } } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { state[2] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 66 -1 0 } } } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\] clr clk 9.800 ns register " "Info: tsu for register lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\] (data pin = clr, clock pin = clk) is 9.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest pin register " "Info: + Longest pin to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clr 1 PIN Pin_5 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = Pin_5; Fanout = 1; PIN Node = 'clr'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clr } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(1.400 ns) 8.700 ns clock~0 2 COMB LC1_A8 3 " "Info: 2: + IC(4.200 ns) + CELL(1.400 ns) = 8.700 ns; Loc. = LC1_A8; Fanout = 3; COMB Node = 'clock~0'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.600 ns" { clr clock~0 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.900 ns) 13.500 ns hhtemp\[0\]~38 3 COMB LC4_A24 3 " "Info: 3: + IC(2.900 ns) + CELL(1.900 ns) = 13.500 ns; Loc. = LC4_A24; Fanout = 3; COMB Node = 'hhtemp\[0\]~38'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.800 ns" { clock~0 hhtemp[0]~38 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 15.500 ns mmtemp\[0\]~6 4 COMB LC2_A24 15 " "Info: 4: + IC(0.600 ns) + CELL(1.400 ns) = 15.500 ns; Loc. = LC2_A24; Fanout = 15; COMB Node = 'mmtemp\[0\]~6'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { hhtemp[0]~38 mmtemp[0]~6 } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.900 ns) 20.000 ns lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~1 5 COMB LC8_A11 7 " "Info: 5: + IC(2.600 ns) + CELL(1.900 ns) = 20.000 ns; Loc. = LC8_A11; Fanout = 7; COMB Node = 'lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|counter_cell\[5\]~1'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.500 ns" { mmtemp[0]~6 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[5]~1 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 317 15 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 22.000 ns lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\] 6 REG LC6_A11 4 " "Info: 6: + IC(0.600 ns) + CELL(1.400 ns) = 22.000 ns; Loc. = LC6_A11; Fanout = 4; REG Node = 'lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.000 ns" { lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[5]~1 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.100 ns 50.45 % " "Info: Total cell delay = 11.100 ns ( 50.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.900 ns 49.55 % " "Info: Total interconnect delay = 10.900 ns ( 49.55 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "22.000 ns" { clr clock~0 hhtemp[0]~38 mmtemp[0]~6 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[5]~1 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" { } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 13.500 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\] 4 REG LC6_A11 4 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC6_A11; Fanout = 4; REG Node = 'lpm_counter:mmtemp_rtl_3\|alt_counter_f10ke:wysi_counter\|q\[5\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "22.000 ns" { clr clock~0 hhtemp[0]~38 mmtemp[0]~6 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[5]~1 lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz lpm_counter:mmtemp_rtl_3|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[6\] hour_display\[3\] 57.100 ns register " "Info: tco from clock clk to destination pin seg7\[6\] through register hour_display\[3\] is 57.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.500 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 13.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK Pin_1 16 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = Pin_1; Fanout = 16; CLK Node = 'clk'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns clk1khz 2 REG LC5_B2 25 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC5_B2; Fanout = 25; REG Node = 'clk1khz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.900 ns" { clk clk1khz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 37 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(0.900 ns) 8.800 ns clk1hz 3 REG LC1_B13 52 " "Info: 3: + IC(3.100 ns) + CELL(0.900 ns) = 8.800 ns; Loc. = LC1_B13; Fanout = 52; REG Node = 'clk1hz'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.000 ns" { clk1khz clk1hz } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 47 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 13.500 ns hour_display\[3\] 4 REG LC8_A20 8 " "Info: 4: + IC(4.700 ns) + CELL(0.000 ns) = 13.500 ns; Loc. = LC8_A20; Fanout = 8; REG Node = 'hour_display\[3\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "4.700 ns" { clk1hz hour_display[3] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns 27.41 % " "Info: Total cell delay = 3.700 ns ( 27.41 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.800 ns 72.59 % " "Info: Total interconnect delay = 9.800 ns ( 72.59 % )" { } { } 0} } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "13.500 ns" { clk clk1khz clk1hz hour_display[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" { } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "42.700 ns + Longest register pin " "Info: + Longest register to pin delay is 42.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour_display\[3\] 1 REG LC8_A20 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A20; Fanout = 8; REG Node = 'hour_display\[3\]'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "" { hour_display[3] } "NODE_NAME" } } } { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 75 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(1.900 ns) 5.500 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 2 COMB LC6_B3 5 " "Info: 2: + IC(3.600 ns) + CELL(1.900 ns) = 5.500 ns; Loc. = LC6_B3; Fanout = 5; COMB Node = 'lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "5.500 ns" { hour_display[3] lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 8.000 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|StageOut\[3\]\[3\]~101 3 COMB LC8_B3 1 " "Info: 3: + IC(0.600 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC8_B3; Fanout = 1; COMB Node = 'lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|StageOut\[3\]\[3\]~101'" { } { { "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" "" "" { Report "I:/Myprg/digital_clk/db/digital_clk_cmp.qrpt" Compiler "digital_clk" "UNKNOWN" "V1" "I:/Myprg/digital_clk/db/digital_clk.quartus_db" { Floorplan "" "" "2.500 ns" { lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00009|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~13 lpm_divide:i_rtl_5|sign_div_unsign:divider|alt_u_div:divider|StageOut[3][3]~101 } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_u_div.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_u_div.tdf" 106 10 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 10.500 ns lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_cs⌨️ 快捷键说明
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