digital_clk.csf.qmsg

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/quartus/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/quartus/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "c:/quartus/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/quartus/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "2 " "Info: Ignored 2 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "2 " "Info: Ignored 2 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WFTM_IGNORED_UNIMPLEMENTABLE_CARRY" "5 " "Warning: Ignored 5 CARRY_SUM primitives" { { "Warning" "WFTM_CARRY_MERGE_FANIN_HDR" "1 " "Warning: Ignored 1 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANIN" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] " "Warning: Can't place logic feeding CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] in single logic cell" { { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 of type CARRY_SUM" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] of type CARRY_SUM" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } {  } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT_HDR" "4 " "Warning: Ignored 4 CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~18 into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~43 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~42 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~19 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~19 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~20 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~20 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] " "Warning: Can't place logic fed by CARRY_SUM primitive lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\] into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~12 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~12 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 " "Warning: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00009\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~13 of type LUT" {  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } { { "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFTM_WANNA_REM_USR_DUPE" "" "Info: Found the following redundant logic cells in design" { { "Info" "IFTM_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41 " "Info: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41" {  } {  } 0} { "Info" "IFTM_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40 " "Info: Node lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40 " "Info: Logic cell lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~40" {  } {  } 0} { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41 " "Info: Logic cell lpm_divide:i_rtl_5\|sign_div_unsign:divider\|alt_u_div:divider\|lpm_add_sub:\$00011\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~41" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "293 " "Info: Implemented 293 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "271 " "Info: Implemented 271 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 14:33:03 2008 " "Info: Processing ended: Tue Dec 02 14:33:03 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Info: Elapsed time: 00:00:15" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 14:33:05 2008 " "Info: Processing started: Tue Dec 02 14:33:05 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off digital_clk -c digital_clk " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off digital_clk -c digital_clk" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "digital_clk EPF10K10LC84-3 " "Info: Selected device EPF10K10LC84-3 for design digital_clk" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0}