digital_clk.csf.qmsg

该工程的主要功能是由VHDL语言实现多功能数字电子时钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 14:32:47 2008 " "Info: Processing started: Tue Dec 02 14:32:47 2008" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off digital_clk -c digital_clk" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "digital_clk.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file digital_clk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 digital_clk-one " "Info: Found design unit 1: digital_clk-one" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "digital_clk-one" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 digital_clk " "Info: Found entity 1: digital_clk" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "digital_clk" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour_display digital_clk.vhd(76) " "Warning: VHDL Process Statement warning at digital_clk.vhd(76): signal hour_display is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min_display digital_clk.vhd(77) " "Warning: VHDL Process Statement warning at digital_clk.vhd(77): signal min_display is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 77 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec_display digital_clk.vhd(78) " "Warning: VHDL Process Statement warning at digital_clk.vhd(78): signal sec_display is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 78 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hour digital_clk.vhd(83) " "Warning: VHDL Process Statement warning at digital_clk.vhd(83): signal hour is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 83 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min digital_clk.vhd(84) " "Warning: VHDL Process Statement warning at digital_clk.vhd(84): signal min is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec digital_clk.vhd(85) " "Warning: VHDL Process Statement warning at digital_clk.vhd(85): signal sec is in statement, but is not in sensitivity list" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 85 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(205) " "Info: VHDL Case Statement information at digital_clk.vhd(205): OTHERS choice is never selected" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 205 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(214) " "Info: VHDL Case Statement information at digital_clk.vhd(214): OTHERS choice is never selected" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 214 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "digital_clk.vhd(233) " "Info: VHDL Case Statement information at digital_clk.vhd(233): OTHERS choice is never selected" {  } { { "I:/Myprg/digital_clk/digital_clk.vhd" "" "" { Text "I:/Myprg/digital_clk/digital_clk.vhd" 233 0 0 } }  } 0}