xlli_lowlev_mac.mac

bootloader for mainstone2 system,main cpu is intel pxa chip.may need edit for your onw system

@*********************************************************************************
@
@ Copyright (C) 2004, Intel Corporation
@
@ This software program is licensed subject to the GNU General Public License
@ (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
@
@*********************************************************************************
@
@                                 xlli_LowLev_mac.mac
@                          MainStone Platform Low Level Macros
@
@ Copyright (c) 2002 by Intel Corp. Hudson MA
@
@ List of macros in this file:
@
@
@ xlli_mapSECTIONS   (Macro) Generates page table entries for MMU
@
@*********************************************************************************




@*********************************************************************************
@      This macro will map a region using 1MB sections
@      Notes:
@             1)You must call xlli_initPageTable before this macro is valid.
@             2) This version of the macro is used when NAMED values are passed to the macro

    .macro    xlli_mapSECTIONS  w1,w2,w3,w4,size,virtual,physical,access,Level1tab

@       $size      = size of region to be mapped
@       $virtual   = starting virtual address of region
@       $physical  = starting physical address of region
@       $access    = access bits for this region
@       $tabl      = physical (base) address of page tables
@       $Level1tab = offset from page table base to level 1 entries

        @ get the page table base address from cp15

        mrc     p15, 0, \w4, c2, c0, 0
        mov     \w4, \w4, LSR #14                         @ Clear the low order 14 bits because cp15...
        mov     \w4, \w4, LSL #14                         @ ...read of these bits are unpredictable

        ldr     \w3,  =\size                              @ get size of bank
        cmp     \w3,  #0
        beq     2                                       @ if size=0, skip

        ldr     \w2,  =\Level1tab + (\virtual:SHR:(20-2)) @ generate table index

        add     \w2,  \w2,   \w4                          @ offset into page table
        mov     \w3,  \w3,   LSR #20                      @ no. of 1MB segments

        ldr     \w1,  =(\physical + \access)              @ create table entry
1:
        str     \w1,  [\w2], #4                           @ store table entry and increment
        add     \w1,  \w1,   #xlli_MemSize_1Mb            @ add section number field
        subs    \w3,  \w3,   #1                           @ decrement loop count
        bne     1
2:

    .endm
@*********************************************************************************
@
@ **************************************************
@ **********                              **********
@ ********** xlli_mapSECTIONS_Var         **********
@ **********                              **********
@ **************************************************
@
@      This macro will map a region using 1MB sections
@      Notes:
@             1)You must call xlli_initPageTable before this macro is valid.
@             2) This version of the macro is used when REGISTER values are passed to the macro

    .macro    xlli_mapSECTIONS_Var  w1,w2,w3,w4,size,virtual,physical,access,Level1tab

@       $size      = size of region to be mapped
@       $virtual   = starting virtual address of region
@       $physical  = starting physical address of region
@       $access    = access bits for this region
@       $tabl      = physical (base) address of page tables
@       $Level1tab = offset from page table base to level 1 entries

        @ get the page table base address from cp15

        mrc     p15, 0, \w4, c2, c0, 0
        mov     \w4, \w4, LSR #14                @ Clear the low order 14 bits because cp15...
        mov     \w4, \w4, LSL #14                @ ...read of these bits are unpredictable

        mov     \w3,  \size                      @ get size of bank
        cmp     \w3,  #0
        beq     2                              @ if size=0, skip

                mov             \w2,  \virtual, LSR #(20-2)
                add             \w2,  \w2, #\Level1tab           @ generate table index

        add     \w2,  \w2,   \w4                 @ offset into page table
        mov     \w3,  \w3,   LSR #20             @ no. of 1MB segments

                add             \w1,  \physical, \access         @ create table entry
1:
        str     \w1,  [\w2], #4                  @ store table entry and increment
        add     \w1,  \w1,   #xlli_MemSize_1Mb   @ add section number field
        subs    \w3,  \w3,   #1                  @ decrement loop count
        bne     1
2:

    .endm
@*********************************************************************************
@
@ **************************************************
@ **********                              **********
@ **********         xlli_cpWait          **********
@ **********                              **********
@ **************************************************
@
@      This macro will arbitrarily read CP15 to create a stall in the pipeline.
@
@  Notes:
@       $Rd      = temporary register to use
@
    .macro    xlli_cpWait  Rd

        MRC     P15, 0, \Rd, C2, C0, 0       @ arbitrary read of CP15
        MOV     \Rd, \Rd                     @ wait for it (foward dependency)
        SUB     PC, PC, #4                   @ branch to next instruction

    .endm

@*********************************************************************************
@
@ **************************************************
@ **********                              **********
@ **********        xlli_retCCSR_L_Val    **********
@ **********                              **********
@ **************************************************
@
@      This macro will read the CCSR's L value and return it in the designated register
@
@  Notes:
@      $Base should contain the base address of the CCSR (virtual or phy)
@
    .macro    xlli_retCCSR_L_Val retval,Base,gp1

        @ read CCCR's value
        ldr     \retval, [\Base, #xlli_CCSR_offset]

        @ mask out irrelevant bits
        ldr     \gp1, =0x1F
        and     \retval, \retval, \gp1

    .endm

@*********************************************************************************
@
@ **************************************************
@ **********                              **********
@ **********       xlli_retCCSR_2N_Val    **********
@ **********                              **********
@ **************************************************
@
@      This macro will read the CCSR and return the 2N value in $retval
@
@  Notes:
@      $Base should contain the base address of the CCSR (virtual or phy)
@
    .macro    xlli_retCCSR_2N_Val retval,Base,gp1

        @ read CCCR's value
        ldr     \retval, [\Base, #xlli_CCSR_offset]

        @ mask out irrelevant bits
        ldr     \gp1, =0x780
        and     \retval, \retval, \gp1
        mov     \retval, \retval LSR #7

    .endm

@*********************************************************************************
@
@ **************************************************
@ **********                              **********
@ **********          xlli_SetLEDs        **********
@ **********                              **********
@ **************************************************
@
@      This macro will dump $ValueReg out to the Mainstone's HEX LEDS
@      via the FPGA for the MAINSTONE PLATFORM ONLY!
@
@  Notes:
@      None
@
   .macro   xlli_SetLEDs ValueReg,tmpreg
        ldr     \tmpreg,    =0x08000000                 @ FPGA PHYS BASE
        str     \ValueReg,  [\tmpreg, #0x10]            @ LED register offset
    .endm

@*********************************************************************************
@*********************************************************************************