实验三.txt

包含交通灯实现等几个vrilog硬件编程的程序

module top(
clk1,
clk2,
reset,
sel,
cnt,
data
);

input         clk1;
input         clk2;
input         reset;
output [2:0]  sel;
output [3:0]  cnt;
output [7:0]  data;

reg    [2:0]  sel;
reg    [3:0]  cnt;
reg    [6:0]  data;

always @(posedge clk1 or negedge reset)
begin
    if (~reset)
        sel <= 3'b0;
    else
        sel <= sel + 1;
end

always @(posedge clk2 or negedge reset)
begin
    if (~reset)
        cnt <= 4'b0;
    else if (cnt == 8)
        cnt <= 1;
    else
        cnt <= cnt + 1;
end

always @(cnt)
begin
        case (cnt)
            4'h0: data <= 7'b011_1111;
            4'h1: data <= 7'b000_0110;
            4'h2: data <= 7'b101_1011;
            4'h3: data <= 7'b100_1111;
            4'h4: data <= 7'b110_0110;
            4'h5: data <= 7'b110_1101;
            4'h6: data <= 7'b111_1101;
            4'h7: data <= 7'b000_0111;
            4'h8: data <= 7'b111_1111;
            4'h9: data <= 7'b110_1111;
            default: data <= 7'b011_1111;
        endcase
end

endmodule





`timescale  1s/1s

module led_test(
);

reg           clk4h;
reg           clk16h;
reg           reset;

wire   [2:0]  selout;
wire   [3:0]  cntout;
wire   [7:0]  dataout;

top     led1(.clk1(clk4h), 
             .clk2(clk16h), 
             .reset(reset), 
             .sel(selout),
             .cnt(cntout),
             .data(dataout));

initial
begin
    clk4h  = 0;
    clk16h = 0;
    reset  = 1;
#20 reset  = 0;
#50 reset  = 1; 
end

always #8   clk4h   = ~clk4h;
always #2   clk16h  = ~clk16h;

endmodule