实验二.txt

包含交通灯实现等几个vrilog硬件编程的程序

module clkdiv(
clk,
reset,
clk16,
clk50,
);

input        clk;
input        reset;
output       clk16;
output       clk50;

reg          clk16;
reg          clk50;

reg    [7:0] cnt16;
reg    [7:0] cnt50;

/* count 8 */
always @(posedge clk or negedge reset)
begin
    if (~reset)
        cnt16 <= 8'b0;
    if (cnt16 == 8'd7)
        cnt16 <= 8'b0;
    else
        cnt16 <= cnt16 + 8'b1;
end

/* count 25 */
always @(posedge clk or negedge reset)
begin
    if (~reset)
        cnt50 <= 8'b0;
    if (cnt50 == 8'd24)
        cnt50 <= 8'b0;
    else
        cnt50 <= cnt50 + 8'b1;
end
    
/* create clk16 */
always @(posedge clk or negedge reset)
begin
    if (~reset)
        clk16 <= 0;
    if (cnt16 == 7)
        clk16 <= ~clk16;
end  

/* create clk50 */
always @(posedge clk or negedge reset)
begin
    if (~reset)
        clk50 <= 0;
    if (cnt50 == 24)
        clk50 <= ~clk50;
end

endmodule






`timescale   10ns/1ns

module test1_clkdiv(
);

reg          clk;
reg          reset;
wire         clk16;
wire         clk50;

clkdiv m000(.clk(clk), .reset(reset), .clk16(clk16), .clk50(clk50));

/* create clock stimulate */
initial
begin
    clk = 0;
end

always #5 clk = ~clk;

/* create reset stimulate */
initial
begin
    reset = 1;
#6  reset = 0;
#50 reset = 1;
end

endmodule