实验一.txt

包含交通灯实现等几个vrilog硬件编程的程序

module test1(a,b,c,data);
    input a,b,c;
    output [7:0] data;
    reg [7:0] data;
    
    always @(a or b or c)
    begin 
    case ({c,b,a})
        3'b000: data=8'b0000_0001;
        3'b001: data=8'b0000_0010;
        3'b010: data=8'b0000_0100;
        3'b011: data=8'b0000_1000;
        3'b100: data=8'b0001_0000;
        3'b101: data=8'b0010_0000;
        3'b110: data=8'b0100_0000;
        3'b111: data=8'b1000_0000;
        default: data=8'b0000_0000;
    endcase
   end 
  
endmodule









`timescale  10us/1us
module test(
);
reg a0,b0,c0;
reg clk;
wire [7:0]dataout;
test1 w2(.a(a0),.b(b0),.c(c0),.data(dataout));
initial
begin 
a0=0;
b0=0;
c0=0;
clk=0;
end
always # 5 clk=~clk;
always @(posedge clk)
begin 
{c0,b0,a0}=$random % 8;
end
endmodule