四.交通灯.txt

包含交通灯实现等几个vrilog硬件编程的程序

module top(
clk1,
clk2,
reset,
sel,
cnt,
data,
lr_red,
lr_yellow,
lr_green,
ud_red,
ud_yellow,
ud_green,
slide_slide
);

input         clk1;
input         clk2;
input         reset;
output [2:0]  sel;
output [4:0]  cnt;
output [7:0]  data;

output        lr_red;
output        lr_yellow;
output        lr_green;
output        ud_red;
output        ud_yellow;
output        ud_green;

output        slide_slide;

reg    [2:0]  sel;
reg    [4:0]  cnt;
reg    [7:0]  data;

reg           lr_red;
reg           lr_yellow;
reg           lr_green;
reg           ud_red;
reg           ud_yellow;
reg           ud_green;

reg    [15:0] cnt_slide;
reg           clk1hz;   // creat one 1Hz clock


reg    [3:0]  h_cnt;
reg    [3:0]  l_cnt;

wire   clkled      = cnt_slide[2];
wire   slide       = cnt_slide[10];
assign slide_slide = cnt_slide[10];

always @(posedge clk2 or negedge reset)
begin
    if (~reset)
        cnt_slide <= 15'b0;
    else
        cnt_slide <= cnt_slide + 1;
end

always @(posedge clk1 or negedge reset)
begin
    if (~reset)
        clk1hz <= 'b0;
    else
        clk1hz <= ~clk1hz;
end

always @(posedge clkled or negedge reset)
begin
    if (~reset)
        sel <= 7;
    else if ( sel == 7)
        sel <= 6;
    else
        sel <= sel + 1;
end

always @(posedge clk1hz or negedge reset)
begin
    if (~reset)
        cnt <= 5'b0;
    else if (cnt == 31)
        cnt <= 5'b0;
    else
        cnt <= cnt + 1;
end

always @(posedge clkled or negedge reset)
begin
    if (~reset)
        data <= 8'b0011_1111;
    else if (sel == 7 )
    begin
        h_cnt = (15 - cnt & 5'b01111)/10;
        case (h_cnt)
            5'h0: data <= 8'b0000_0000;
            5'h1: data <= 8'b0000_0110;
            5'h2: data <= 8'b0101_1011;
            5'h3: data <= 8'b0100_1111;
            5'h4: data <= 8'b0110_0110;
            5'h5: data <= 8'b0110_1101;
            5'h6: data <= 8'b0111_1101;
            5'h7: data <= 8'b0000_0111;
            5'h8: data <= 8'b0111_1111;
            5'h9: data <= 8'b0110_1111;
            default: data <= 8'b0011_1111;
        endcase
    end
    else if (sel == 6 )
    begin
        l_cnt = (15 - cnt & 5'b01111)%10;
        case (l_cnt)
            5'h0: data <= 8'b0011_1111;
            5'h1: data <= 8'b0000_0110;
            5'h2: data <= 8'b0101_1011;
            5'h3: data <= 8'b0100_1111;
            5'h4: data <= 8'b0110_0110;
            5'h5: data <= 8'b0110_1101;
            5'h6: data <= 8'b0111_1101;
            5'h7: data <= 8'b0000_0111;
            5'h8: data <= 8'b0111_1111;
            5'h9: data <= 8'b0110_1111;
            default: data <= 8'b0011_1111;
        endcase
    end
   
end

always @(posedge clk2 or negedge reset)
begin
    if (~reset)
        begin
            lr_red <= 1;   
            lr_yellow <= 0;
            lr_green <= 0; 
            ud_red <= 1;   
            ud_yellow <=0;
            ud_green <= 0;
        end
    else if ( cnt < 10)
        begin
            lr_red <= 0;   
            lr_yellow <= 0;
            lr_green <= 1; 
            ud_red <= 1;   
            ud_yellow <=0;
            ud_green <= 0;
        end
    else if ( cnt < 13)
        begin
            lr_red <= 0;   
            lr_yellow <= 0;
            lr_green <= slide; 
            ud_red <= 1;   
            ud_yellow <=0;
            ud_green <= 0;
        end
    else if ( cnt < 16)
        begin
            lr_red <= 0;   
            lr_yellow <= slide;
            lr_green <= 0; 
            ud_red <= 1;   
            ud_yellow <=0;
            ud_green <= 0;
        end
    else if ( cnt < 26)
        begin
            lr_red <= 1;   
            lr_yellow <= 0;
            lr_green <= 0; 
            ud_red <= 0;   
            ud_yellow <=0;
            ud_green <= 1;
        end
    else if ( cnt < 29)
        begin
            lr_red <= 1;   
            lr_yellow <= 0;
            lr_green <= 0; 
            ud_red <= 0;   
            ud_yellow <=0;
            ud_green <= slide;
        end
    else if ( cnt <= 31)
        begin
            lr_red <= 1;   
            lr_yellow <= 0;
            lr_green <= 0; 
            ud_red <= 0;   
            ud_yellow <= slide;
            ud_green <= 0;
        end       
end

endmodule 



测试
`timescale  1s/1s

module led_test(
);

reg           clk4h;
reg           clk16h;
reg           reset;

wire   [2:0]  selout;
wire   [4:0]  cntout;
wire   [7:0]  dataout;

wire          lr_red;
wire          lr_yellow;
wire          lr_green;
wire          ud_red;
wire          ud_yellow;
wire          ud_green;
wire          slide_slide;


top     led1(.clk1(clk4h), 
             .clk2(clk16h), 
             .reset(reset), 
             .sel(selout),
             .cnt(cntout),
             .data(dataout),
             .lr_red(lr_red),   
             .lr_yellow(lr_yellow),
             .lr_green(lr_green), 
             .ud_red(ud_red),   
             .ud_yellow(ud_yellow),
             .ud_green(ud_green),
             . slide_slide(slide_slide));

initial
begin
    clk4h  = 0;
    clk16h = 0;
    reset  = 1;
#20 reset  = 0;
#50 reset  = 1; 
end

always #200   clk4h   = ~clk4h;
always #2   clk16h  = ~clk16h;

endmodule