seg71.tan.qmsg

一些Verilog学习程序B

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt_scan\[3\] register cnt_scan\[12\] 201.09 MHz 4.973 ns Internal " "Info: Clock \"clk\" has Internal fmax of 201.09 MHz between source register \"cnt_scan\[3\]\" and destination register \"cnt_scan\[12\]\" (period= 4.973 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.264 ns + Longest register register " "Info: + Longest register to register delay is 4.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[3\] 1 REG LC_X3_Y4_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt_scan[3] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.978 ns) 1.870 ns cnt_scan\[3\]~99 2 COMB LC_X3_Y4_N5 2 " "Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X3_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan\[3\]~99'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.870 ns" { cnt_scan[3] cnt_scan[3]~99 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.993 ns cnt_scan\[4\]~98 3 COMB LC_X3_Y4_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X3_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan\[4\]~98'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[3]~99 cnt_scan[4]~98 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.116 ns cnt_scan\[5\]~97 4 COMB LC_X3_Y4_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X3_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan\[5\]~97'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[4]~98 cnt_scan[5]~97 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.239 ns cnt_scan\[6\]~96 5 COMB LC_X3_Y4_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan\[6\]~96'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.123 ns" { cnt_scan[5]~97 cnt_scan[6]~96 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 2.638 ns cnt_scan\[7\]~95 6 COMB LC_X3_Y4_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan\[7\]~95'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { cnt_scan[6]~96 cnt_scan[7]~95 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.264 ns cnt_scan\[12\] 7 REG LC_X4_Y4_N4 2 " "Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.626 ns" { cnt_scan[7]~95 cnt_scan[12] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.372 ns ( 79.08 % ) " "Info: Total cell delay = 3.372 ns ( 79.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.892 ns ( 20.92 % ) " "Info: Total interconnect delay = 0.892 ns ( 20.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.264 ns" { cnt_scan[3] cnt_scan[3]~99 cnt_scan[4]~98 cnt_scan[5]~97 cnt_scan[6]~96 cnt_scan[7]~95 cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.264 ns" { cnt_scan[3] cnt_scan[3]~99 cnt_scan[4]~98 cnt_scan[5]~97 cnt_scan[6]~96 cnt_scan[7]~95 cnt_scan[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_scan\[12\] 2 REG LC_X4_Y4_N4 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_scan\[3\] 2 REG LC_X3_Y4_N5 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.264 ns" { cnt_scan[3] cnt_scan[3]~99 cnt_scan[4]~98 cnt_scan[5]~97 cnt_scan[6]~96 cnt_scan[7]~95 cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.264 ns" { cnt_scan[3] cnt_scan[3]~99 cnt_scan[4]~98 cnt_scan[5]~97 cnt_scan[6]~96 cnt_scan[7]~95 cnt_scan[12] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 1.626ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[12] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[3] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] cnt_scan\[15\] 10.521 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"cnt_scan\[15\]\" is 10.521 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_scan\[15\] 2 REG LC_X4_Y4_N7 15 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_scan[15] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[15] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.797 ns + Longest register pin " "Info: + Longest register to pin delay is 6.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_scan\[15\] 1 REG LC_X4_Y4_N7 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan\[15\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt_scan[15] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.510 ns) + CELL(0.740 ns) 2.250 ns Decoder1~92 2 COMB LC_X5_Y4_N0 2 " "Info: 2: + IC(1.510 ns) + CELL(0.740 ns) = 2.250 ns; Loc. = LC_X5_Y4_N0; Fanout = 2; COMB Node = 'Decoder1~92'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.250 ns" { cnt_scan[15] Decoder1~92 } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.225 ns) + CELL(2.322 ns) 6.797 ns dataout\[5\] 3 PIN PIN_78 0 " "Info: 3: + IC(2.225 ns) + CELL(2.322 ns) = 6.797 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.547 ns" { Decoder1~92 dataout[5] } "NODE_NAME" } } { "seg71.v" "" { Text "E:/Verilog/接口实验/7段数码管/seg71/seg71.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.062 ns ( 45.05 % ) " "Info: Total cell delay = 3.062 ns ( 45.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.735 ns ( 54.95 % ) " "Info: Total interconnect delay = 3.735 ns ( 54.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.797 ns" { cnt_scan[15] Decoder1~92 dataout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.797 ns" { cnt_scan[15] Decoder1~92 dataout[5] } { 0.000ns 1.510ns 2.225ns } { 0.000ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_scan[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_scan[15] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.797 ns" { cnt_scan[15] Decoder1~92 dataout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.797 ns" { cnt_scan[15] Decoder1~92 dataout[5] } { 0.000ns 1.510ns 2.225ns } { 0.000ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:51:58 2009 " "Info: Processing ended: Sun Jan 11 21:51:58 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}