seg71.tan.rpt

一些Verilog学习程序B

+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------+
; tco                                                                        ;
+-------+--------------+------------+--------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To         ; From Clock ;
+-------+--------------+------------+--------------+------------+------------+
; N/A   ; None         ; 10.521 ns  ; cnt_scan[15] ; dataout[5] ; clk        ;
; N/A   ; None         ; 10.465 ns  ; cnt_scan[15] ; dataout[7] ; clk        ;
; N/A   ; None         ; 10.379 ns  ; cnt_scan[14] ; dataout[5] ; clk        ;
; N/A   ; None         ; 10.324 ns  ; cnt_scan[14] ; dataout[7] ; clk        ;
; N/A   ; None         ; 10.099 ns  ; cnt_scan[15] ; en[4]      ; clk        ;
; N/A   ; None         ; 10.089 ns  ; cnt_scan[15] ; dataout[1] ; clk        ;
; N/A   ; None         ; 10.009 ns  ; cnt_scan[13] ; dataout[5] ; clk        ;
; N/A   ; None         ; 9.981 ns   ; cnt_scan[15] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.974 ns   ; cnt_scan[15] ; dataout[2] ; clk        ;
; N/A   ; None         ; 9.958 ns   ; cnt_scan[15] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.954 ns   ; cnt_scan[13] ; dataout[7] ; clk        ;
; N/A   ; None         ; 9.952 ns   ; cnt_scan[14] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.947 ns   ; cnt_scan[14] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.839 ns   ; cnt_scan[14] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.827 ns   ; cnt_scan[14] ; dataout[2] ; clk        ;
; N/A   ; None         ; 9.823 ns   ; cnt_scan[13] ; en[6]      ; clk        ;
; N/A   ; None         ; 9.816 ns   ; cnt_scan[14] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.791 ns   ; cnt_scan[13] ; dataout[6] ; clk        ;
; N/A   ; None         ; 9.636 ns   ; cnt_scan[14] ; en[6]      ; clk        ;
; N/A   ; None         ; 9.601 ns   ; cnt_scan[13] ; en[5]      ; clk        ;
; N/A   ; None         ; 9.582 ns   ; cnt_scan[13] ; en[4]      ; clk        ;
; N/A   ; None         ; 9.577 ns   ; cnt_scan[13] ; dataout[1] ; clk        ;
; N/A   ; None         ; 9.469 ns   ; cnt_scan[13] ; en[3]      ; clk        ;
; N/A   ; None         ; 9.452 ns   ; cnt_scan[13] ; dataout[2] ; clk        ;
; N/A   ; None         ; 9.362 ns   ; cnt_scan[13] ; dataout[3] ; clk        ;
; N/A   ; None         ; 9.361 ns   ; cnt_scan[13] ; dataout[4] ; clk        ;
; N/A   ; None         ; 9.289 ns   ; cnt_scan[15] ; en[6]      ; clk        ;
; N/A   ; None         ; 9.284 ns   ; cnt_scan[14] ; en[5]      ; clk        ;
; N/A   ; None         ; 9.243 ns   ; cnt_scan[15] ; en[5]      ; clk        ;
; N/A   ; None         ; 9.037 ns   ; cnt_scan[14] ; dataout[3] ; clk        ;
; N/A   ; None         ; 9.036 ns   ; cnt_scan[14] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.934 ns   ; cnt_scan[15] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.933 ns   ; cnt_scan[15] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.908 ns   ; cnt_scan[15] ; en[2]      ; clk        ;
; N/A   ; None         ; 8.907 ns   ; cnt_scan[15] ; en[1]      ; clk        ;
; N/A   ; None         ; 8.900 ns   ; cnt_scan[15] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.766 ns   ; cnt_scan[14] ; en[2]      ; clk        ;
; N/A   ; None         ; 8.765 ns   ; cnt_scan[14] ; en[1]      ; clk        ;
; N/A   ; None         ; 8.758 ns   ; cnt_scan[14] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.739 ns   ; cnt_scan[13] ; en[7]      ; clk        ;
; N/A   ; None         ; 8.552 ns   ; cnt_scan[14] ; en[7]      ; clk        ;
; N/A   ; None         ; 8.396 ns   ; cnt_scan[13] ; en[2]      ; clk        ;
; N/A   ; None         ; 8.396 ns   ; cnt_scan[13] ; en[1]      ; clk        ;
; N/A   ; None         ; 8.388 ns   ; cnt_scan[13] ; en[0]      ; clk        ;
; N/A   ; None         ; 8.205 ns   ; cnt_scan[15] ; en[7]      ; clk        ;
+-------+--------------+------------+--------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 21:51:58 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg71 -c seg71
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 201.09 MHz between source register "cnt_scan[3]" and destination register "cnt_scan[12]" (period= 4.973 ns)
    Info: + Longest register to register delay is 4.264 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X3_Y4_N5; Fanout = 2; COMB Node = 'cnt_scan[3]~99'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X3_Y4_N6; Fanout = 2; COMB Node = 'cnt_scan[4]~98'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X3_Y4_N7; Fanout = 2; COMB Node = 'cnt_scan[5]~97'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; COMB Node = 'cnt_scan[6]~96'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; COMB Node = 'cnt_scan[7]~95'
        Info: 7: + IC(0.000 ns) + CELL(1.626 ns) = 4.264 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
        Info: Total cell delay = 3.372 ns ( 79.08 % )
        Info: Total interconnect delay = 0.892 ns ( 20.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N4; Fanout = 2; REG Node = 'cnt_scan[12]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y4_N5; Fanout = 3; REG Node = 'cnt_scan[3]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "dataout[5]" through register "cnt_scan[15]" is 10.521 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.797 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 15; REG Node = 'cnt_scan[15]'
        Info: 2: + IC(1.510 ns) + CELL(0.740 ns) = 2.250 ns; Loc. = LC_X5_Y4_N0; Fanout = 2; COMB Node = 'Decoder1~92'
        Info: 3: + IC(2.225 ns) + CELL(2.322 ns) = 6.797 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'dataout[5]'
        Info: Total cell delay = 3.062 ns ( 45.05 % )
        Info: Total interconnect delay = 3.735 ns ( 54.95 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 21:51:58 2009
    Info: Elapsed time: 00:00:02