ledwater.tan.qmsg

一些Verilog学习程序B

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 6 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[16\] register dataout\[5\]~reg0 136.89 MHz 7.305 ns Internal " "Info: Clock \"clk\" has Internal fmax of 136.89 MHz between source register \"cnt\[16\]\" and destination register \"dataout\[5\]~reg0\" (period= 7.305 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.596 ns + Longest register register " "Info: + Longest register to register delay is 6.596 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[16\] 1 REG LC_X5_Y2_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N9; Fanout = 3; REG Node = 'cnt\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[16] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.244 ns) + CELL(0.914 ns) 2.158 ns Equal0~234 2 COMB LC_X6_Y2_N8 1 " "Info: 2: + IC(1.244 ns) + CELL(0.914 ns) = 2.158 ns; Loc. = LC_X6_Y2_N8; Fanout = 1; COMB Node = 'Equal0~234'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.158 ns" { cnt[16] Equal0~234 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.663 ns Equal0~235 3 COMB LC_X6_Y2_N9 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.663 ns; Loc. = LC_X6_Y2_N9; Fanout = 1; COMB Node = 'Equal0~235'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~234 Equal0~235 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.914 ns) 4.674 ns Equal0~236 4 COMB LC_X7_Y2_N8 3 " "Info: 4: + IC(1.097 ns) + CELL(0.914 ns) = 4.674 ns; Loc. = LC_X7_Y2_N8; Fanout = 3; COMB Node = 'Equal0~236'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.011 ns" { Equal0~235 Equal0~236 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.679 ns) + CELL(1.243 ns) 6.596 ns dataout\[5\]~reg0 5 REG LC_X7_Y2_N0 2 " "Info: 5: + IC(0.679 ns) + CELL(1.243 ns) = 6.596 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.922 ns" { Equal0~236 dataout[5]~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.271 ns ( 49.59 % ) " "Info: Total cell delay = 3.271 ns ( 49.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.325 ns ( 50.41 % ) " "Info: Total interconnect delay = 3.325 ns ( 50.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.596 ns" { cnt[16] Equal0~234 Equal0~235 Equal0~236 dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.596 ns" { cnt[16] Equal0~234 Equal0~235 Equal0~236 dataout[5]~reg0 } { 0.000ns 1.244ns 0.305ns 1.097ns 0.679ns } { 0.000ns 0.914ns 0.200ns 0.914ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns dataout\[5\]~reg0 2 REG LC_X7_Y2_N0 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[16\] 2 REG LC_X5_Y2_N9 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N9; Fanout = 3; REG Node = 'cnt\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[16] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[16] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[16] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.596 ns" { cnt[16] Equal0~234 Equal0~235 Equal0~236 dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.596 ns" { cnt[16] Equal0~234 Equal0~235 Equal0~236 dataout[5]~reg0 } { 0.000ns 1.244ns 0.305ns 1.097ns 0.679ns } { 0.000ns 0.914ns 0.200ns 0.914ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[16] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[5\] dataout\[5\]~reg0 7.994 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[5\]\" through register \"dataout\[5\]~reg0\" is 7.994 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 26 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns dataout\[5\]~reg0 2 REG LC_X7_Y2_N0 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.270 ns + Longest register pin " "Info: + Longest register to pin delay is 4.270 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout\[5\]~reg0 1 REG LC_X7_Y2_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout\[5\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { dataout[5]~reg0 } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.948 ns) + CELL(2.322 ns) 4.270 ns dataout\[5\] 2 PIN PIN_56 0 " "Info: 2: + IC(1.948 ns) + CELL(2.322 ns) = 4.270 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'dataout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.270 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 54.38 % ) " "Info: Total cell delay = 2.322 ns ( 54.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.948 ns ( 45.62 % ) " "Info: Total interconnect delay = 1.948 ns ( 45.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.270 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.270 ns" { dataout[5]~reg0 dataout[5] } { 0.000ns 1.948ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk dataout[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout dataout[5]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.270 ns" { dataout[5]~reg0 dataout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.270 ns" { dataout[5]~reg0 dataout[5] } { 0.000ns 1.948ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 22:01:09 2009 " "Info: Processing ended: Sun Jan 11 22:01:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}