ledwater.map.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 22:00:48 2009 " "Info: Processing started: Sun Jan 11 22:00:48 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ledwater -c ledwater" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ledwater.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ledwater.v" { { "Info" "ISGN_ENTITY_NAME" "1 ledwater " "Info: Found entity 1: ledwater" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "ledwater " "Info: Elaborating entity \"ledwater\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 8 ledwater.v(16) " "Warning (10230): Verilog HDL assignment warning at ledwater.v(16): truncated value with size 12 to match size of target (8)" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 23 ledwater.v(19) " "Warning (10230): Verilog HDL assignment warning at ledwater.v(19): truncated value with size 32 to match size of target (23)" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout ledwater.v(12) " "Warning (10240): Verilog HDL Always Construct warning at ledwater.v(12): inferring latch(es) for variable \"dataout\", which holds its previous value in one or more paths through the always construct" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 12 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[4\] ledwater.v(7) " "Info (10041): Verilog HDL or VHDL info at ledwater.v(7): inferred latch for \"dataout\[4\]\"" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 7 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "dataout\[3\] ledwater.v(7) " "Info (10041): Verilog HDL or VHDL info at ledwater.v(7): inferred latch for \"dataout\[3\]\"" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 7 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "dataout\[2\]~reg0 High " "Info: Power-up level of register \"dataout\[2\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dataout\[2\]~reg0 data_in VCC " "Warning: Reduced register \"dataout\[2\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "dataout\[1\]~reg0 High " "Info: Power-up level of register \"dataout\[1\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dataout\[1\]~reg0 data_in VCC " "Warning: Reduced register \"dataout\[1\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "dataout\[0\]~reg0 High " "Info: Power-up level of register \"dataout\[0\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dataout\[0\]~reg0 data_in VCC " "Warning: Reduced register \"dataout\[0\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[0\] VCC " "Warning: Pin \"dataout\[0\]\" stuck at VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[1\] VCC " "Warning: Pin \"dataout\[1\]\" stuck at VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[2\] VCC " "Warning: Pin \"dataout\[2\]\" stuck at VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[3\] VCC " "Warning: Pin \"dataout\[3\]\" stuck at VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[4\] VCC " "Warning: Pin \"dataout\[4\]\" stuck at VCC" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "ledwater.v" "" { Text "E:/Verilog/接口实验/跑马灯/ledwater.v" 14 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 22:00:50 2009 " "Info: Processing ended: Sun Jan 11 22:00:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}