ledwater.map.summary

一些Verilog学习程序B

Analysis & Synthesis Status : Successful - Sun Jan 11 22:00:50 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : ledwater
Top-level Entity Name : ledwater
Family : MAX II
Total logic elements : 34
Total pins : 10
Total virtual pins : 0
UFM blocks : 0