ledwater.tan.rpt

一些Verilog学习程序B

; N/A                                     ; 211.64 MHz ( period = 4.725 ns )                    ; cnt[9]  ; cnt[17]         ; clk        ; clk      ; None                        ; None                      ; 4.016 ns                ;
; N/A                                     ; 211.64 MHz ( period = 4.725 ns )                    ; cnt[9]  ; cnt[21]         ; clk        ; clk      ; None                        ; None                      ; 4.016 ns                ;
; N/A                                     ; 212.22 MHz ( period = 4.712 ns )                    ; cnt[9]  ; cnt[22]         ; clk        ; clk      ; None                        ; None                      ; 4.003 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[7]          ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[8]          ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[9]          ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[10]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[11]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[11] ; cnt[20]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[11] ; cnt[19]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[11] ; cnt[18]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[11] ; cnt[17]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[11] ; cnt[21]         ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[1]  ; cnt[12]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[1]  ; cnt[13]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[1]  ; cnt[14]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[1]  ; cnt[15]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[1]  ; cnt[16]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 215.47 MHz ( period = 4.641 ns )                    ; cnt[11] ; cnt[22]         ; clk        ; clk      ; None                        ; None                      ; 3.932 ns                ;
; N/A                                     ; 217.11 MHz ( period = 4.606 ns )                    ; cnt[5]  ; cnt[9]          ; clk        ; clk      ; None                        ; None                      ; 3.897 ns                ;
; N/A                                     ; 217.11 MHz ( period = 4.606 ns )                    ; cnt[5]  ; cnt[10]         ; clk        ; clk      ; None                        ; None                      ; 3.897 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;                 ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------+
; tco                                                                           ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To         ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A   ; None         ; 7.994 ns   ; dataout[5]~reg0 ; dataout[5] ; clk        ;
; N/A   ; None         ; 6.832 ns   ; dataout[7]~reg0 ; dataout[7] ; clk        ;
; N/A   ; None         ; 6.813 ns   ; dataout[6]~reg0 ; dataout[6] ; clk        ;
+-------+--------------+------------+-----------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 22:01:07 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ledwater -c ledwater
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 136.89 MHz between source register "cnt[16]" and destination register "dataout[5]~reg0" (period= 7.305 ns)
    Info: + Longest register to register delay is 6.596 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N9; Fanout = 3; REG Node = 'cnt[16]'
        Info: 2: + IC(1.244 ns) + CELL(0.914 ns) = 2.158 ns; Loc. = LC_X6_Y2_N8; Fanout = 1; COMB Node = 'Equal0~234'
        Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.663 ns; Loc. = LC_X6_Y2_N9; Fanout = 1; COMB Node = 'Equal0~235'
        Info: 4: + IC(1.097 ns) + CELL(0.914 ns) = 4.674 ns; Loc. = LC_X7_Y2_N8; Fanout = 3; COMB Node = 'Equal0~236'
        Info: 5: + IC(0.679 ns) + CELL(1.243 ns) = 6.596 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: Total cell delay = 3.271 ns ( 49.59 % )
        Info: Total interconnect delay = 3.325 ns ( 50.41 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout[5]~reg0'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N9; Fanout = 3; REG Node = 'cnt[16]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "dataout[5]" through register "dataout[5]~reg0" is 7.994 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 26; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.270 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y2_N0; Fanout = 2; REG Node = 'dataout[5]~reg0'
        Info: 2: + IC(1.948 ns) + CELL(2.322 ns) = 4.270 ns; Loc. = PIN_56; Fanout = 0; PIN Node = 'dataout[5]'
        Info: Total cell delay = 2.322 ns ( 54.38 % )
        Info: Total interconnect delay = 1.948 ns ( 45.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 22:01:09 2009
    Info: Elapsed time: 00:00:03