serial.fit.eqn

一些Verilog学习程序B

--A1L46 is reduce_or~5285 at SEXP89
A1L46 = EXP(rxd_buf[2] & !rxd_buf[3] & !rxd_buf[7] & rxd_buf[5] & rxd_buf[4] & !rxd_buf[6] & !rxd_buf[0]);


--A1L56 is reduce_or~5286 at SEXP91
A1L56 = EXP(!rxd_buf[3] & !rxd_buf[1] & !rxd_buf[7] & rxd_buf[5] & rxd_buf[4] & !rxd_buf[6] & !rxd_buf[0]);


--A1L66 is reduce_or~5291 at LC86
A1L66_p1_out = A1L36 & A1L46 & A1L56;
A1L66_p0_out = A1L36 & A1L46 & A1L56 & !rxd_buf[3] & rxd_buf[1] & !rxd_buf[7] & !rxd_buf[5] & !rxd_buf[4] & rxd_buf[6] & !rxd_buf[0];
A1L66_p2_out = A1L36 & A1L46 & A1L56 & !rxd_buf[2] & rxd_buf[3] & !rxd_buf[1] & !rxd_buf[7] & rxd_buf[5] & rxd_buf[4] & !rxd_buf[6];
A1L66_p3_out = A1L36 & A1L46 & A1L56 & !rxd_buf[2] & !rxd_buf[3] & rxd_buf[1] & !rxd_buf[7] & !rxd_buf[5] & !rxd_buf[4] & rxd_buf[6];
A1L66_p4_out = A1L36 & A1L46 & A1L56 & !rxd_buf[3] & !rxd_buf[1] & !rxd_buf[7] & !rxd_buf[5] & !rxd_buf[4] & rxd_buf[6] & rxd_buf[0];
A1L66_or_out = A1L66_p0_out # A1L66_p2_out # A1L66_p3_out # A1L66_p4_out;
A1L66 = A1L66_p1_out $ A1L66_or_out;


--A1L76 is reduce_or~5294 at SEXP94
A1L76 = EXP(!rxd_buf[1] & !rxd_buf[0]);


--A1L86 is reduce_or~5295 at SEXP82
A1L86 = EXP(rxd_buf[1] & rxd_buf[0]);


--A1L96 is reduce_or~5300 at LC91
A1L96_p1_out = !rxd_buf[2] & !rxd_buf[6] & rxd_buf[4] & !rxd_buf[1] & rxd_buf[5] & !rxd_buf[7] & !rxd_buf[0];
A1L96_p2_out = !rxd_buf[6] & rxd_buf[4] & rxd_buf[1] & rxd_buf[5] & !rxd_buf[7] & !rxd_buf[0] & !rxd_buf[3];
A1L96_p3_out = !rxd_buf[2] & rxd_buf[6] & !rxd_buf[4] & !rxd_buf[5] & !rxd_buf[7] & !rxd_buf[3] & A1L76;
A1L96_p4_out = rxd_buf[2] & rxd_buf[6] & !rxd_buf[4] & !rxd_buf[5] & !rxd_buf[7] & !rxd_buf[3] & A1L86;
A1L96_or_out = A1L96_p1_out # A1L96_p2_out # A1L96_p3_out # A1L96_p4_out;
A1L96 = !(A1L96_or_out);


--key_entry1 is key_entry1 at LC4
key_entry1_p1_out = key_entry1 & !key_entry2 & rst;
key_entry1_p2_out = !key_entry2 & rst & !key_input & !cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[18];
key_entry1_or_out = key_entry1_p1_out # key_entry1_p2_out;
key_entry1_reg_input = key_entry1_or_out;
key_entry1 = DFFE(key_entry1_reg_input, GLOBAL(clk), , , );


--key_entry2 is key_entry2 at LC64
key_entry2_p1_out = !key_entry1 & !key_entry2;
key_entry2_p2_out = key_entry2 & send_state[2] & send_state[0] & send_state[1] & !state_tras[2] & !state_tras[1] & !state_tras[0] & !state_tras[3];
key_entry2_or_out = key_entry2_p1_out # key_entry2_p2_out;
key_entry2_reg_input = !(key_entry2_or_out);
key_entry2 = DFFE(key_entry2_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[3] is state_tras[3] at LC38
state_tras[3]_p1_out = state_tras[2] & state_tras[1] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2;
state_tras[3]_or_out = state_tras[3]_p1_out;
state_tras[3]_reg_input = state_tras[3]_or_out;
state_tras[3] = TFFE(state_tras[3]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L221 is trasstart~45 at SEXP35
A1L221 = EXP(state_tras[3] & state_tras[2] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2);


--A1L421 is trasstart~47 at SEXP36
A1L421 = EXP(state_tras[0] & state_tras[1]);


--trasstart is trasstart at LC47
trasstart_p0_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & state_tras[2] & key_entry2 & A1L421;
trasstart_p1_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & state_tras[3] & !state_tras[2] & state_tras[1] & key_entry2;
trasstart_p2_out = A1L221 & trasstart;
trasstart_p4_out = !state_tras[3] & !state_tras[2] & !state_tras[1] & key_entry2 & A1L321 & !state_tras[0];
trasstart_or_out = trasstart_p0_out # trasstart_p1_out # trasstart_p2_out # trasstart_p4_out;
trasstart_reg_input = trasstart_or_out;
trasstart = DFFE(trasstart_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[0] is div8_tras_reg[0] at LC41
div8_tras_reg[0]_or_out = trasstart;
div8_tras_reg[0]_reg_input = div8_tras_reg[0]_or_out;
div8_tras_reg[0] = TFFE(div8_tras_reg[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[1] is div8_tras_reg[1] at LC40
div8_tras_reg[1]_p1_out = div8_tras_reg[0] & trasstart;
div8_tras_reg[1]_or_out = div8_tras_reg[1]_p1_out;
div8_tras_reg[1]_reg_input = div8_tras_reg[1]_or_out;
div8_tras_reg[1] = TFFE(div8_tras_reg[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--div8_tras_reg[2] is div8_tras_reg[2] at LC36
div8_tras_reg[2]_p1_out = div8_tras_reg[1] & div8_tras_reg[0] & trasstart;
div8_tras_reg[2]_or_out = div8_tras_reg[2]_p1_out;
div8_tras_reg[2]_reg_input = div8_tras_reg[2]_or_out;
div8_tras_reg[2] = TFFE(div8_tras_reg[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[0] is state_tras[0] at LC123
state_tras[0]_p1_out = key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_p2_out = send_state[2] & send_state[0] & send_state[1] & !state_tras[2] & !state_tras[1] & !state_tras[3] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_p4_out = !state_tras[2] & !state_tras[1] & !state_tras[3] & key_entry2 & !trasstart & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
state_tras[0]_or_out = state_tras[0] # state_tras[0]_p2_out # state_tras[0]_p4_out;
state_tras[0]_reg_input = state_tras[0]_p1_out $ state_tras[0]_or_out;
state_tras[0] = DFFE(state_tras[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[1] is state_tras[1] at LC34
state_tras[1]_p1_out = state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2;
state_tras[1]_or_out = state_tras[1]_p1_out;
state_tras[1]_reg_input = state_tras[1]_or_out;
state_tras[1] = TFFE(state_tras[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--state_tras[2] is state_tras[2] at LC33
state_tras[2]_p1_out = state_tras[1] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2;
state_tras[2]_or_out = state_tras[2]_p1_out;
state_tras[2]_reg_input = state_tras[2]_or_out;
state_tras[2] = TFFE(state_tras[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--txd_buf[6] is txd_buf[6] at LC120
txd_buf[6]_p0_out = div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & state_tras[2] & txd_buf[6] & !state_tras[3];
txd_buf[6]_p1_out = send_state[1] & send_state[2] & state_tras[0] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & state_tras[2] & txd_buf[6];
txd_buf[6]_p2_out = state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & txd_buf[6] & !state_tras[3];
txd_buf[6]_p4_out = state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & txd_buf[6] & !state_tras[3];
txd_buf[6]_or_out = A1L251 # txd_buf[6]_p0_out # txd_buf[6]_p1_out # txd_buf[6]_p2_out # txd_buf[6]_p4_out;
txd_buf[6]_reg_input = txd_buf[6]_or_out;
txd_buf[6] = TFFE(txd_buf[6]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L441 is txd_buf[5]~355 at SEXP60
A1L441 = EXP(!state_tras[2] & !state_tras[1] & !state_tras[0]);


--A1L541 is txd_buf[5]~356 at SEXP118
A1L541 = EXP(key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1]);


--A1L641 is txd_buf[5]~357 at SEXP121
A1L641 = EXP(send_state[1] & send_state[2]);


--txd_buf[5] is txd_buf[5] at LC114
txd_buf[5]_p0_out = !key_entry2 & key_entry1;
txd_buf[5]_p1_out = A1L541 & txd_buf[5];
txd_buf[5]_p2_out = A1L641 & key_entry2 & state_tras[0] & state_tras[1] & state_tras[3] & state_tras[2] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
txd_buf[5]_p4_out = txd_buf[5] & state_tras[3] & state_tras[2] & A1L521;
txd_buf[5]_or_out = A1L741 # txd_buf[5]_p0_out # txd_buf[5]_p1_out # txd_buf[5]_p2_out # txd_buf[5]_p4_out;
txd_buf[5]_reg_input = txd_buf[5]_or_out;
txd_buf[5] = DFFE(txd_buf[5]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L041 is txd_buf[4]~367 at SEXP61
A1L041 = EXP(!state_tras[1] & !state_tras[2]);


--txd_buf[4] is txd_buf[4] at LC52
txd_buf[4]_p0_out = state_tras[3] & key_entry2 & !txd_buf[4] & A1L041;
txd_buf[4]_p1_out = !state_tras[1] & !state_tras[3] & key_entry2 & !state_tras[2] & !state_tras[0] & !txd_buf[4];
txd_buf[4]_p2_out = !key_entry2 & !txd_buf[4] & !key_entry1;
txd_buf[4]_p4_out = !state_tras[3] & key_entry2 & A1L441 & !txd_buf[5] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
txd_buf[4]_or_out = A1L141 # txd_buf[4]_p0_out # txd_buf[4]_p1_out # txd_buf[4]_p2_out # txd_buf[4]_p4_out;
txd_buf[4]_reg_input = !(txd_buf[4]_or_out);
txd_buf[4] = DFFE(txd_buf[4]_reg_input, clkbaud8x, GLOBAL(rst), , );


--txd_buf[3] is txd_buf[3] at LC55
txd_buf[3]_p0_out = key_entry2 & state_tras[3] & state_tras[2] & txd_buf[3] & A1L621;
txd_buf[3]_p1_out = key_entry2 & state_tras[3] & !state_tras[2] & state_tras[1] & txd_buf[3];
txd_buf[3]_p2_out = !key_entry2 & txd_buf[3] & !key_entry1;
txd_buf[3]_p4_out = key_entry2 & !state_tras[3] & A1L441 & txd_buf[4] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
txd_buf[3]_or_out = A1L831 # txd_buf[3]_p0_out # txd_buf[3]_p1_out # txd_buf[3]_p2_out # txd_buf[3]_p4_out;
txd_buf[3]_reg_input = txd_buf[3]_or_out;
txd_buf[3] = DFFE(txd_buf[3]_reg_input, clkbaud8x, GLOBAL(rst), , );


--txd_buf[2] is txd_buf[2] at LC59
txd_buf[2]_p0_out = txd_buf[2] & !send_state[1] & txd_buf[3];
txd_buf[2]_p1_out = txd_buf[2] & A1L35;
txd_buf[2]_p2_out = state_tras[0] & state_tras[3] & !state_tras[2] & txd_buf[2];
txd_buf[2]_p4_out = state_tras[3] & state_tras[2] & txd_buf[2] & !send_state[1];
txd_buf[2]_or_out = A1L531 # txd_buf[2]_p0_out # txd_buf[2]_p1_out # txd_buf[2]_p2_out # txd_buf[2]_p4_out;
txd_buf[2]_reg_input = txd_buf[2]_or_out;
txd_buf[2] = DFFE(txd_buf[2]_reg_input, clkbaud8x, GLOBAL(rst), , );


--txd_buf[1] is txd_buf[1] at LC50
txd_buf[1]_p0_out = !key_entry2 & key_entry1;
txd_buf[1]_p1_out = A1L441 & txd_buf[2] & key_entry2 & !state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
txd_buf[1]_p2_out = A1L841 & txd_buf[1];
txd_buf[1]_p4_out = state_tras[3] & txd_buf[1] & A1L621 & state_tras[2];
txd_buf[1]_or_out = A1L131 # txd_buf[1]_p0_out # txd_buf[1]_p1_out # txd_buf[1]_p2_out # txd_buf[1]_p4_out;
txd_buf[1]_reg_input = txd_buf[1]_or_out;
txd_buf[1] = DFFE(txd_buf[1]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L37 is rtl~4791 at LC60
A1L37_p1_out = !state_tras[2] & !state_tras[1] & !state_tras[0];
A1L37_p2_out = state_tras[2] & state_tras[1] & state_tras[0] & div8_tras_reg[1] & div8_tras_reg[0] & div8_tras_reg[2] & send_state[1] & send_state[2];
A1L37_p3_out = state_tras[2] & state_tras[1] & state_tras[0] & div8_tras_reg[1] & div8_tras_reg[0] & div8_tras_reg[2] & !send_state[1] & !send_state[2] & send_state[0];
A1L37_or_out = A1L37_p1_out # A1L37_p2_out # A1L37_p3_out # !state_tras[3];
A1L37 = A1L37_or_out;


--A1L47 is rtl~4797 at LC35
A1L47_p1_out = state_tras[0] & key_entry2;
A1L47_p2_out = key_entry2 & state_tras[3];
A1L47_p3_out = key_entry2 & state_tras[2];
A1L47_p4_out = key_entry2 & state_tras[1];
A1L47_or_out = A1L47_p1_out # A1L47_p2_out # A1L47_p3_out # A1L47_p4_out;
A1L47 = A1L47_or_out;


--A1L77 is rtl~4807 at LC122
A1L77_p0_out = key_entry2 & !state_tras[3] & state_tras[2];
A1L77_p1_out = key_entry1 & !key_entry2;
A1L77_p2_out = key_entry2 & state_tras[3] & !state_tras[0] & !state_tras[2] & !state_tras[1];
A1L77_p3_out = key_entry2 & state_tras[0] & !state_tras[2] & !state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L77_p4_out = key_entry2 & state_tras[0] & state_tras[2] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L77_or_out = A1L87 # A1L77_p0_out # A1L77_p1_out # A1L77_p2_out # A1L77_p3_out # A1L77_p4_out;
A1L77 = A1L77_or_out;


--txd_buf[0] is txd_buf[0] at LC61
txd_buf[0]_p1_out = A1L37 & A1L47 & A1L77 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & A1L57 & A1L67;
txd_buf[0]_p2_out = A1L37 & A1L47 & !txd_buf[0] & A1L57 & A1L67;
txd_buf[0]_p4_out = !A1L77 & !txd_buf[0];
txd_buf[0]_or_out = txd_buf[0]_p1_out # txd_buf[0]_p2_out # txd_buf[0]_p4_out;
txd_buf[0]_reg_input = !(txd_buf[0]_or_out);
txd_buf[0] = DFFE(txd_buf[0]_reg_input, clkbaud8x, GLOBAL(rst), , );


--A1L451 is txd_reg~60 at SEXP37
A1L451 = EXP(div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2);


--txd_reg is txd_reg at LC43
txd_reg_p0_out = state_tras[3] & A1L241 & !txd_reg;
txd_reg_p1_out = A1L941 & div8_tras_reg[2] & div8_tras_reg[0] & !state_tras[3] & div8_tras_reg[1] & !txd_buf[0] & key_entry2;
txd_reg_p2_out = div8_tras_reg[2] & div8_tras_reg[0] & !state_tras[3] & div8_tras_reg[1] & key_entry2 & A1L321 & !state_tras[2] & !state_tras[1] & trasstart & !state_tras[0];
txd_reg_or_out = A1L551 # txd_reg_p0_out # txd_reg_p1_out # txd_reg_p2_out;
txd_reg_reg_input = !(txd_reg_or_out);
txd_reg = DFFE(txd_reg_reg_input, clkbaud8x, , rst, );


--A1L07 is reduce_or~5302 at LC87
A1L07_p1_out = !rxd_buf[3] & !rxd_buf[7] & !rxd_buf[4] & !rxd_buf[5] & rxd_buf[6] & rxd_buf[2] & rxd_buf[1] & !rxd_buf[0];
A1L07_p2_out = !rxd_buf[3] & !rxd_buf[7] & !rxd_buf[4] & !rxd_buf[5] & rxd_buf[6] & !rxd_buf[2] & rxd_buf[0];
A1L07 = A1L07_p1_out # A1L07_p2_out;


--A1L251 is txd_buf[6]~405 at LC119
A1L251_p0_out = !state_tras[0] & !state_tras[1] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & !state_tras[2] & txd_buf[6];
A1L251_p1_out = !send_state[1] & state_tras[0] & state_tras[1] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & state_tras[2] & !txd_buf[6];
A1L251_p2_out = state_tras[0] & state_tras[1] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & state_tras[2] & !txd_buf[6] & !send_state[2];
A1L251_p3_out = state_tras[0] & !state_tras[1] & state_tras[3] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & key_entry2 & !state_tras[2] & !txd_buf[6];
A1L251_p4_out = !key_entry2 & !txd_buf[6] & key_entry1;
A1L251 = A1L251_p0_out # A1L251_p1_out # A1L251_p2_out # A1L251_p3_out # A1L251_p4_out;


--A1L741 is txd_buf[5]~411 at LC113
A1L741_p0_out = txd_buf[6] & key_entry2 & !state_tras[3] & A1L051 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L741_p1_out = !state_tras[0] & txd_buf[6] & txd_buf[5];
A1L741_p2_out = !state_tras[0] & txd_buf[6] & key_entry2 & !state_tras[1] & state_tras[3] & !state_tras[2] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L741_p3_out = !state_tras[0] & txd_buf[5] & !state_tras[1] & !state_tras[3] & !state_tras[2];
A1L741_p4_out = txd_buf[5] & state_tras[1] & state_tras[3] & !state_tras[2];
A1L741 = A1L741_p0_out # A1L741_p1_out # A1L741_p2_out # A1L741_p3_out # A1L741_p4_out;


--A1L141 is txd_buf[4]~417 at LC51
A1L141_p1_out = !txd_buf[5] & !state_tras[1] & state_tras[3] & key_entry2 & !state_tras[2] & !state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L141_p2_out = state_tras[1] & state_tras[3] & key_entry2 & state_tras[2] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L141_p3_out = !txd_buf[5] & !state_tras[3] & key_entry2 & !txd_buf[4];
A1L141_p4_out = key_entry2 & !txd_buf[4] & A1L35;
A1L141 = A1L141_p1_out # A1L141_p2_out # A1L141_p3_out # A1L141_p4_out;


--A1L731 is txd_buf[3]~422 at LC53
A1L731_p1_out = key_entry2 & txd_buf[3] & A1L35;
A1L731_p2_out = key_entry2 & txd_buf[3] & txd_buf[4] & !state_tras[0];
A1L731_p3_out = txd_buf[3] & state_tras[3] & state_tras[2] & send_state[0] & !send_state[2] & !key_entry1;
A1L731 = A1L731_p1_out # A1L731_p2_out # A1L731_p3_out;


--A1L831 is txd_buf[3]~426 at LC54
A1L831_p0_out = !state_tras[3] & !state_tras[2] & txd_buf[3] & key_entry2 & !state_tras[0] & !state_tras[1];
A1L831_p1_out = state_tras[3] & state_tras[2] & txd_buf[3] & !send_state[0] & send_state[2] & !send_state[1] & !key_entry1;
A1L831_p2_out = state_tras[3] & !state_tras[2] & txd_buf[4] & key_entry2 & !state_tras[0] & !state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L831_p3_out = state_tras[3] & state_tras[2] & send_state[0] & !send_state[2] & key_entry2 & state_tras[0] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L831_p4_out = state_tras[3] & state_tras[2] & !send_state[0] & send_state[2] & !send_state[1] & key_entry2 & state_tras[0] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L831 = A1L731 # A1L831_p0_out # A1L831_p1_out # A1L831_p2_out # A1L831_p3_out # A1L831_p4_out;