serial.hier_info

一些Verilog学习程序B

|serial
clk => cnt_delay[18].CLK
clk => cnt_delay[17].CLK
clk => cnt_delay[16].CLK
clk => cnt_delay[15].CLK
clk => cnt_delay[14].CLK
clk => cnt_delay[13].CLK
clk => cnt_delay[12].CLK
clk => cnt_delay[11].CLK
clk => cnt_delay[10].CLK
clk => cnt_delay[9].CLK
clk => cnt_delay[8].CLK
clk => cnt_delay[7].CLK
clk => cnt_delay[6].CLK
clk => cnt_delay[5].CLK
clk => cnt_delay[4].CLK
clk => cnt_delay[3].CLK
clk => cnt_delay[2].CLK
clk => cnt_delay[1].CLK
clk => cnt_delay[0].CLK
clk => start_delaycnt.CLK
clk => key_entry1.CLK
clk => div_reg[15].CLK
clk => div_reg[14].CLK
clk => div_reg[13].CLK
clk => div_reg[12].CLK
clk => div_reg[11].CLK
clk => div_reg[10].CLK
clk => div_reg[9].CLK
clk => div_reg[8].CLK
clk => div_reg[7].CLK
clk => div_reg[6].CLK
clk => div_reg[5].CLK
clk => div_reg[4].CLK
clk => div_reg[3].CLK
clk => div_reg[2].CLK
clk => div_reg[1].CLK
clk => div_reg[0].CLK
clk => clkbaud8x.CLK
clk => cnt_delay[19].CLK
rst => clkbaud8x~1.OUTPUTSELECT
rst => key_entry1~3.OUTPUTSELECT
rst => cnt_delay~40.OUTPUTSELECT
rst => cnt_delay~41.OUTPUTSELECT
rst => cnt_delay~42.OUTPUTSELECT
rst => cnt_delay~43.OUTPUTSELECT
rst => cnt_delay~44.OUTPUTSELECT
rst => cnt_delay~45.OUTPUTSELECT
rst => cnt_delay~46.OUTPUTSELECT
rst => cnt_delay~47.OUTPUTSELECT
rst => cnt_delay~48.OUTPUTSELECT
rst => cnt_delay~49.OUTPUTSELECT
rst => cnt_delay~50.OUTPUTSELECT
rst => cnt_delay~51.OUTPUTSELECT
rst => cnt_delay~52.OUTPUTSELECT
rst => cnt_delay~53.OUTPUTSELECT
rst => cnt_delay~54.OUTPUTSELECT
rst => cnt_delay~55.OUTPUTSELECT
rst => cnt_delay~56.OUTPUTSELECT
rst => cnt_delay~57.OUTPUTSELECT
rst => cnt_delay~58.OUTPUTSELECT
rst => cnt_delay~59.OUTPUTSELECT
rst => start_delaycnt~3.OUTPUTSELECT
rst => trasstart.ACLR
rst => txd_buf[7].ACLR
rst => txd_buf[6].ACLR
rst => txd_buf[5].ACLR
rst => txd_buf[4].ACLR
rst => txd_buf[3].ACLR
rst => txd_buf[2].ACLR
rst => txd_buf[1].ACLR
rst => txd_buf[0].ACLR
rst => state_tras[3].ACLR
rst => state_tras[2].ACLR
rst => state_tras[1].ACLR
rst => state_tras[0].ACLR
rst => send_state[2].ACLR
rst => send_state[1].ACLR
rst => send_state[0].ACLR
rst => key_entry2.ACLR
rst => txd_reg.PRESET
rst => div_reg~16.OUTPUTSELECT
rst => div_reg~17.OUTPUTSELECT
rst => div_reg~18.OUTPUTSELECT
rst => div_reg~19.OUTPUTSELECT
rst => div_reg~20.OUTPUTSELECT
rst => div_reg~21.OUTPUTSELECT
rst => div_reg~22.OUTPUTSELECT
rst => div_reg~23.OUTPUTSELECT
rst => div_reg~24.OUTPUTSELECT
rst => div_reg~25.OUTPUTSELECT
rst => div_reg~26.OUTPUTSELECT
rst => div_reg~27.OUTPUTSELECT
rst => div_reg~28.OUTPUTSELECT
rst => div_reg~29.OUTPUTSELECT
rst => div_reg~30.OUTPUTSELECT
rst => div_reg~31.OUTPUTSELECT
rst => div8_rec_reg[1].ACLR
rst => div8_rec_reg[0].ACLR
rst => div8_rec_reg[2].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[0].ACLR
rst => div8_tras_reg[2].ACLR
rst => rxd_reg2.ACLR
rst => rxd_buf[7].ACLR
rst => rxd_buf[6].ACLR
rst => rxd_buf[5].ACLR
rst => rxd_buf[4].ACLR
rst => rxd_buf[3].ACLR
rst => rxd_buf[2].ACLR
rst => rxd_buf[1].ACLR
rst => rxd_buf[0].ACLR
rst => state_rec[3].ACLR
rst => state_rec[2].ACLR
rst => state_rec[1].ACLR
rst => state_rec[0].ACLR
rst => recstart.ACLR
rst => recstart_tmp.ACLR
rst => rxd_reg1.ACLR
rxd => rxd_reg1.DATAIN
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>
seg_data[0] <= WideOr15.DB_MAX_OUTPUT_PORT_TYPE
seg_data[1] <= WideOr14.DB_MAX_OUTPUT_PORT_TYPE
seg_data[2] <= WideOr13.DB_MAX_OUTPUT_PORT_TYPE
seg_data[3] <= WideOr12.DB_MAX_OUTPUT_PORT_TYPE
seg_data[4] <= WideOr11.DB_MAX_OUTPUT_PORT_TYPE
seg_data[5] <= WideOr10.DB_MAX_OUTPUT_PORT_TYPE
seg_data[6] <= WideOr9.DB_MAX_OUTPUT_PORT_TYPE
seg_data[7] <= WideOr8.DB_MAX_OUTPUT_PORT_TYPE
key_input => key_entry1~0.OUTPUTSELECT
key_input => always0~0.IN0
lowbit <= <GND>