serial.map.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 25 23:53:06 2009 " "Info: Processing started: Mon May 25 23:53:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off serial -c serial " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial -c serial" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serial.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file serial.v" { { "Info" "ISGN_ENTITY_NAME" "1 serial " "Info: Found entity 1: serial" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 12 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serial " "Info: Elaborating entity \"serial\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 serial.v(69) " "Warning (10230): Verilog HDL assignment warning at serial.v(69): truncated value with size 32 to match size of target (20)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 serial.v(104) " "Warning (10230): Verilog HDL assignment warning at serial.v(104): truncated value with size 32 to match size of target (16)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 serial.v(122) " "Warning (10230): Verilog HDL assignment warning at serial.v(122): truncated value with size 32 to match size of target (3)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 serial.v(130) " "Warning (10230): Verilog HDL assignment warning at serial.v(130): truncated value with size 32 to match size of target (3)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(174) " "Warning (10230): Verilog HDL assignment warning at serial.v(174): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(186) " "Warning (10230): Verilog HDL assignment warning at serial.v(186): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(193) " "Warning (10230): Verilog HDL assignment warning at serial.v(193): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 193 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(200) " "Warning (10230): Verilog HDL assignment warning at serial.v(200): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 200 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(207) " "Warning (10230): Verilog HDL assignment warning at serial.v(207): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(214) " "Warning (10230): Verilog HDL assignment warning at serial.v(214): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(221) " "Warning (10230): Verilog HDL assignment warning at serial.v(221): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 221 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(228) " "Warning (10230): Verilog HDL assignment warning at serial.v(228): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 228 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(235) " "Warning (10230): Verilog HDL assignment warning at serial.v(235): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 235 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(242) " "Warning (10230): Verilog HDL assignment warning at serial.v(242): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 242 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(247) " "Warning (10230): Verilog HDL assignment warning at serial.v(247): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 247 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 serial.v(248) " "Warning (10230): Verilog HDL assignment warning at serial.v(248): truncated value with size 32 to match size of target (3)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 248 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(270) " "Warning (10230): Verilog HDL assignment warning at serial.v(270): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 270 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(296) " "Warning (10230): Verilog HDL assignment warning at serial.v(296): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 296 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 serial.v(305) " "Warning (10230): Verilog HDL assignment warning at serial.v(305): truncated value with size 32 to match size of target (4)" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 305 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "txd_buf\[7\] data_in GND " "Warning: Reduced register \"txd_buf\[7\]\" with stuck data_in port to stuck value GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 151 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 18 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lowbit GND " "Warning: Pin \"lowbit\" stuck at GND" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 22 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 151 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "199 " "Info: Implemented 199 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "177 " "Info: Implemented 177 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 25 23:53:17 2009 " "Info: Processing ended: Mon May 25 23:53:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}