serial.tan.qmsg

一些Verilog学习程序B

{ "Info" "ITDB_TSU_RESULT" "cnt_delay\[8\] rst clk 4.744 ns register " "Info: tsu for register \"cnt_delay\[8\]\" (data pin = \"rst\", clock pin = \"clk\") is 4.744 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.759 ns + Longest pin register " "Info: + Longest pin to register delay is 7.759 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_26 45 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_26; Fanout = 45; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.677 ns) + CELL(0.511 ns) 4.320 ns cnt_delay\[11\]~1017 2 COMB LC_X6_Y1_N3 20 " "Info: 2: + IC(2.677 ns) + CELL(0.511 ns) = 4.320 ns; Loc. = LC_X6_Y1_N3; Fanout = 20; COMB Node = 'cnt_delay\[11\]~1017'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.188 ns" { rst cnt_delay[11]~1017 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.679 ns) + CELL(1.760 ns) 7.759 ns cnt_delay\[8\] 3 REG LC_X4_Y1_N8 5 " "Info: 3: + IC(1.679 ns) + CELL(1.760 ns) = 7.759 ns; Loc. = LC_X4_Y1_N8; Fanout = 5; REG Node = 'cnt_delay\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.439 ns" { cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.403 ns ( 43.86 % ) " "Info: Total cell delay = 3.403 ns ( 43.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.356 ns ( 56.14 % ) " "Info: Total interconnect delay = 4.356 ns ( 56.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.759 ns" { rst cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.759 ns" { rst rst~combout cnt_delay[11]~1017 cnt_delay[8] } { 0.000ns 0.000ns 2.677ns 1.679ns } { 0.000ns 1.132ns 0.511ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_delay\[8\] 2 REG LC_X4_Y1_N8 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N8; Fanout = 5; REG Node = 'cnt_delay\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[8] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.759 ns" { rst cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.759 ns" { rst rst~combout cnt_delay[11]~1017 cnt_delay[8] } { 0.000ns 0.000ns 2.677ns 1.679ns } { 0.000ns 1.132ns 0.511ns 1.760ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[8] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[4\] rxd_buf\[4\] 15.813 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[4\]\" through register \"rxd_buf\[4\]\" is 15.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.390 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkbaud8x 2 REG LC_X2_Y3_N2 40 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N2; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkbaud8x } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 7.390 ns rxd_buf\[4\] 3 REG LC_X5_Y4_N5 10 " "Info: 3: + IC(2.748 ns) + CELL(0.918 ns) = 7.390 ns; Loc. = LC_X5_Y4_N5; Fanout = 10; REG Node = 'rxd_buf\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.666 ns" { clkbaud8x rxd_buf[4] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 281 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.67 % ) " "Info: Total cell delay = 3.375 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.015 ns ( 54.33 % ) " "Info: Total interconnect delay = 4.015 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x rxd_buf[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x rxd_buf[4] } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 281 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.047 ns + Longest register pin " "Info: + Longest register to pin delay is 8.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd_buf\[4\] 1 REG LC_X5_Y4_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N5; Fanout = 10; REG Node = 'rxd_buf\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd_buf[4] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 281 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.914 ns) 1.849 ns WideOr11~734 2 COMB LC_X5_Y4_N8 1 " "Info: 2: + IC(0.935 ns) + CELL(0.914 ns) = 1.849 ns; Loc. = LC_X5_Y4_N8; Fanout = 1; COMB Node = 'WideOr11~734'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.849 ns" { rxd_buf[4] WideOr11~734 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.200 ns) 3.657 ns WideOr11~735 3 COMB LC_X6_Y4_N7 1 " "Info: 3: + IC(1.608 ns) + CELL(0.200 ns) = 3.657 ns; Loc. = LC_X6_Y4_N7; Fanout = 1; COMB Node = 'WideOr11~735'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { WideOr11~734 WideOr11~735 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.740 ns) 5.119 ns WideOr11~737 4 COMB LC_X6_Y4_N3 1 " "Info: 4: + IC(0.722 ns) + CELL(0.740 ns) = 5.119 ns; Loc. = LC_X6_Y4_N3; Fanout = 1; COMB Node = 'WideOr11~737'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.462 ns" { WideOr11~735 WideOr11~737 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 319 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.606 ns) + CELL(2.322 ns) 8.047 ns seg_data\[4\] 5 PIN PIN_81 0 " "Info: 5: + IC(0.606 ns) + CELL(2.322 ns) = 8.047 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'seg_data\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.928 ns" { WideOr11~737 seg_data[4] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.176 ns ( 51.90 % ) " "Info: Total cell delay = 4.176 ns ( 51.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.871 ns ( 48.10 % ) " "Info: Total interconnect delay = 3.871 ns ( 48.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.047 ns" { rxd_buf[4] WideOr11~734 WideOr11~735 WideOr11~737 seg_data[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.047 ns" { rxd_buf[4] WideOr11~734 WideOr11~735 WideOr11~737 seg_data[4] } { 0.000ns 0.935ns 1.608ns 0.722ns 0.606ns } { 0.000ns 0.914ns 0.200ns 0.740ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x rxd_buf[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x rxd_buf[4] } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.047 ns" { rxd_buf[4] WideOr11~734 WideOr11~735 WideOr11~737 seg_data[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.047 ns" { rxd_buf[4] WideOr11~734 WideOr11~735 WideOr11~737 seg_data[4] } { 0.000ns 0.935ns 1.608ns 0.722ns 0.606ns } { 0.000ns 0.914ns 0.200ns 0.740ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "rxd_reg1 rxd clk 2.570 ns register " "Info: th for register \"rxd_reg1\" (data pin = \"rxd\", clock pin = \"clk\") is 2.570 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.390 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkbaud8x 2 REG LC_X2_Y3_N2 40 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N2; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkbaud8x } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 7.390 ns rxd_reg1 3 REG LC_X2_Y4_N3 2 " "Info: 3: + IC(2.748 ns) + CELL(0.918 ns) = 7.390 ns; Loc. = LC_X2_Y4_N3; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.666 ns" { clkbaud8x rxd_reg1 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.67 % ) " "Info: Total cell delay = 3.375 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.015 ns ( 54.33 % ) " "Info: Total interconnect delay = 4.015 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 40 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.041 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rxd 1 PIN PIN_5 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_5; Fanout = 1; PIN Node = 'rxd'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rxd } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.318 ns) + CELL(0.591 ns) 5.041 ns rxd_reg1 2 REG LC_X2_Y4_N3 2 " "Info: 2: + IC(3.318 ns) + CELL(0.591 ns) = 5.041 ns; Loc. = LC_X2_Y4_N3; Fanout = 2; REG Node = 'rxd_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.909 ns" { rxd rxd_reg1 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 34.18 % ) " "Info: Total cell delay = 1.723 ns ( 34.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.318 ns ( 65.82 % ) " "Info: Total interconnect delay = 3.318 ns ( 65.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.041 ns" { rxd rxd_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.041 ns" { rxd rxd~combout rxd_reg1 } { 0.000ns 0.000ns 3.318ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x rxd_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x rxd_reg1 } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.041 ns" { rxd rxd_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.041 ns" { rxd rxd~combout rxd_reg1 } { 0.000ns 0.000ns 3.318ns } { 0.000ns 1.132ns 0.591ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 25 23:53:34 2009 " "Info: Processing ended: Mon May 25 23:53:34 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}