serial.tan.qmsg

一些Verilog学习程序B

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkbaud8x " "Info: Detected ripple clock \"clkbaud8x\" as buffer" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 33 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt_delay\[4\] register cnt_delay\[8\] 103.97 MHz 9.618 ns Internal " "Info: Clock \"clk\" has Internal fmax of 103.97 MHz between source register \"cnt_delay\[4\]\" and destination register \"cnt_delay\[8\]\" (period= 9.618 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.909 ns + Longest register register " "Info: + Longest register to register delay is 8.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_delay\[4\] 1 REG LC_X4_Y1_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N4; Fanout = 3; REG Node = 'cnt_delay\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt_delay[4] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.864 ns) + CELL(0.511 ns) 2.375 ns always0~142 2 COMB LC_X3_Y1_N4 1 " "Info: 2: + IC(1.864 ns) + CELL(0.511 ns) = 2.375 ns; Loc. = LC_X3_Y1_N4; Fanout = 1; COMB Node = 'always0~142'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.375 ns" { cnt_delay[4] always0~142 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.885 ns) + CELL(0.200 ns) 4.460 ns always0~145 3 COMB LC_X6_Y1_N1 2 " "Info: 3: + IC(1.885 ns) + CELL(0.200 ns) = 4.460 ns; Loc. = LC_X6_Y1_N1; Fanout = 2; COMB Node = 'always0~145'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.085 ns" { always0~142 always0~145 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.965 ns Equal0~78 4 COMB LC_X6_Y1_N2 3 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.965 ns; Loc. = LC_X6_Y1_N2; Fanout = 3; COMB Node = 'Equal0~78'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { always0~145 Equal0~78 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.470 ns cnt_delay\[11\]~1017 5 COMB LC_X6_Y1_N3 20 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.470 ns; Loc. = LC_X6_Y1_N3; Fanout = 20; COMB Node = 'cnt_delay\[11\]~1017'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~78 cnt_delay[11]~1017 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.679 ns) + CELL(1.760 ns) 8.909 ns cnt_delay\[8\] 6 REG LC_X4_Y1_N8 5 " "Info: 6: + IC(1.679 ns) + CELL(1.760 ns) = 8.909 ns; Loc. = LC_X4_Y1_N8; Fanout = 5; REG Node = 'cnt_delay\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.439 ns" { cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.871 ns ( 32.23 % ) " "Info: Total cell delay = 2.871 ns ( 32.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.038 ns ( 67.77 % ) " "Info: Total interconnect delay = 6.038 ns ( 67.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.909 ns" { cnt_delay[4] always0~142 always0~145 Equal0~78 cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.909 ns" { cnt_delay[4] always0~142 always0~145 Equal0~78 cnt_delay[11]~1017 cnt_delay[8] } { 0.000ns 1.864ns 1.885ns 0.305ns 0.305ns 1.679ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_delay\[8\] 2 REG LC_X4_Y1_N8 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N8; Fanout = 5; REG Node = 'cnt_delay\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[8] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt_delay\[4\] 2 REG LC_X4_Y1_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N4; Fanout = 3; REG Node = 'cnt_delay\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt_delay[4] } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[8] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.909 ns" { cnt_delay[4] always0~142 always0~145 Equal0~78 cnt_delay[11]~1017 cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.909 ns" { cnt_delay[4] always0~142 always0~145 Equal0~78 cnt_delay[11]~1017 cnt_delay[8] } { 0.000ns 1.864ns 1.885ns 0.305ns 0.305ns 1.679ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.200ns 1.760ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[8] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt_delay[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt_delay[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "key_entry1 key_entry2 clk 2.235 ns " "Info: Found hold time violation between source  pin or register \"key_entry1\" and destination pin or register \"key_entry2\" for clock \"clk\" (Hold time is 2.235 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.042 ns + Largest " "Info: + Largest clock skew is 4.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.390 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkbaud8x 2 REG LC_X2_Y3_N2 40 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N2; Fanout = 40; REG Node = 'clkbaud8x'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clkbaud8x } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 7.390 ns key_entry2 3 REG LC_X4_Y2_N0 19 " "Info: 3: + IC(2.748 ns) + CELL(0.918 ns) = 7.390 ns; Loc. = LC_X4_Y2_N0; Fanout = 19; REG Node = 'key_entry2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.666 ns" { clkbaud8x key_entry2 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.67 % ) " "Info: Total cell delay = 3.375 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.015 ns ( 54.33 % ) " "Info: Total interconnect delay = 4.015 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 39; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns key_entry1 2 REG LC_X5_Y2_N3 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; REG Node = 'key_entry1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk key_entry1 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_entry1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_entry1 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_entry1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_entry1 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.652 ns - Shortest register register " "Info: - Shortest register to register delay is 1.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_entry1 1 REG LC_X5_Y2_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; REG Node = 'key_entry1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_entry1 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.372 ns) + CELL(0.280 ns) 1.652 ns key_entry2 2 REG LC_X4_Y2_N0 19 " "Info: 2: + IC(1.372 ns) + CELL(0.280 ns) = 1.652 ns; Loc. = LC_X4_Y2_N0; Fanout = 19; REG Node = 'key_entry2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.652 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 16.95 % ) " "Info: Total cell delay = 0.280 ns ( 16.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.372 ns ( 83.05 % ) " "Info: Total interconnect delay = 1.372 ns ( 83.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.652 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.652 ns" { key_entry1 key_entry2 } { 0.000ns 1.372ns } { 0.000ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "serial.v" "" { Text "E:/EPM240学习板B/Verilog/接口实验/串口/serial.v" 49 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.390 ns" { clk clkbaud8x key_entry2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.390 ns" { clk clk~combout clkbaud8x key_entry2 } { 0.000ns 0.000ns 1.267ns 2.748ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_entry1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_entry1 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.652 ns" { key_entry1 key_entry2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.652 ns" { key_entry1 key_entry2 } { 0.000ns 1.372ns } { 0.000ns 0.280ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}