serial.map.eqn

一些Verilog学习程序B

--A1L431 is txd_buf[4]~417
A1L431_p1_out = !txd_buf[5] & !state_tras[1] & state_tras[3] & key_entry2 & !state_tras[2] & !state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L431_p2_out = state_tras[1] & state_tras[3] & key_entry2 & state_tras[2] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L431_p3_out = !txd_buf[5] & !state_tras[3] & key_entry2 & !txd_buf[4];
A1L431_p4_out = key_entry2 & !txd_buf[4] & A1L94;
A1L431 = A1L431_p1_out # A1L431_p2_out # A1L431_p3_out # A1L431_p4_out;


--A1L031 is txd_buf[3]~422
A1L031_p1_out = key_entry2 & txd_buf[3] & A1L94;
A1L031_p2_out = key_entry2 & txd_buf[3] & txd_buf[4] & !state_tras[0];
A1L031_p3_out = txd_buf[3] & state_tras[3] & state_tras[2] & send_state[0] & !send_state[2] & !key_entry1;
A1L031 = A1L031_p1_out # A1L031_p2_out # A1L031_p3_out;


--A1L131 is txd_buf[3]~426
A1L131_p0_out = !state_tras[3] & !state_tras[2] & txd_buf[3] & key_entry2 & !state_tras[0] & !state_tras[1];
A1L131_p1_out = state_tras[3] & state_tras[2] & txd_buf[3] & !send_state[0] & send_state[2] & !send_state[1] & !key_entry1;
A1L131_p2_out = state_tras[3] & !state_tras[2] & txd_buf[4] & key_entry2 & !state_tras[0] & !state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L131_p3_out = state_tras[3] & state_tras[2] & send_state[0] & !send_state[2] & key_entry2 & state_tras[0] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L131_p4_out = state_tras[3] & state_tras[2] & !send_state[0] & send_state[2] & !send_state[1] & key_entry2 & state_tras[0] & state_tras[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L131 = A1L031 # A1L131_p0_out # A1L131_p1_out # A1L131_p2_out # A1L131_p3_out # A1L131_p4_out;


--A1L621 is txd_buf[2]~432
A1L621_p0_out = txd_buf[2] & !state_tras[1] & !state_tras[3] & !state_tras[2] & !state_tras[0];
A1L621_p1_out = !key_entry2 & key_entry1;
A1L621_p2_out = txd_buf[2] & !key_entry2;
A1L621_p3_out = txd_buf[2] & state_tras[1] & state_tras[3] & !state_tras[0];
A1L621_p4_out = txd_buf[2] & state_tras[3] & state_tras[2] & !state_tras[0];
A1L621 = A1L621_p0_out # A1L621_p1_out # A1L621_p2_out # A1L621_p3_out # A1L621_p4_out;


--A1L721 is txd_buf[2]~438
A1L721_p0_out = !state_tras[1] & state_tras[3] & !state_tras[2] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & txd_buf[3];
A1L721_p1_out = state_tras[0] & !state_tras[1] & state_tras[3] & txd_buf[2];
A1L721_p2_out = state_tras[0] & !state_tras[3] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & txd_buf[3];
A1L721_p3_out = state_tras[1] & !state_tras[3] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & txd_buf[3];
A1L721_p4_out = !state_tras[3] & state_tras[2] & key_entry2 & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & txd_buf[3];
A1L721 = A1L621 # A1L721_p0_out # A1L721_p1_out # A1L721_p2_out # A1L721_p3_out # A1L721_p4_out;


--A1L821 is txd_buf[2]~444
A1L821_p0_out = state_tras[3] & state_tras[2] & txd_buf[2] & !send_state[2] & send_state[0];
A1L821_p1_out = !state_tras[1] & txd_buf[3] & txd_buf[2];
A1L821_p2_out = key_entry2 & state_tras[1] & state_tras[3] & state_tras[2] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !send_state[1];
A1L821_p3_out = key_entry2 & state_tras[1] & state_tras[3] & state_tras[2] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !send_state[2] & send_state[0];
A1L821_p4_out = key_entry2 & !state_tras[1] & state_tras[3] & !state_tras[2] & state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L821 = A1L721 # A1L821_p0_out # A1L821_p1_out # A1L821_p2_out # A1L821_p3_out # A1L821_p4_out;


--A1L421 is txd_buf[1]~450
A1L421_p0_out = txd_buf[1] & state_tras[1] & state_tras[3] & !state_tras[2];
A1L421_p1_out = txd_buf[2] & !state_tras[0] & txd_buf[1];
A1L421_p2_out = txd_buf[2] & !state_tras[0] & key_entry2 & !state_tras[1] & state_tras[3] & !state_tras[2] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L421_p3_out = state_tras[0] & key_entry2 & state_tras[1] & state_tras[3] & state_tras[2] & !send_state[2] & send_state[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1];
A1L421_p4_out = !state_tras[0] & txd_buf[1] & !state_tras[1] & !state_tras[3] & !state_tras[2];
A1L421 = A1L421_p0_out # A1L421_p1_out # A1L421_p2_out # A1L421_p3_out # A1L421_p4_out;


--A1L441 is txd_reg~71
A1L441_p1_out = !state_tras[2] & !state_tras[3] & !txd_reg & !state_tras[1] & !state_tras[0];
A1L441_p2_out = !state_tras[2] & state_tras[3] & !state_tras[1] & !state_tras[0] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !txd_buf[0] & key_entry2;
A1L441_p3_out = !txd_reg & A1L341;
A1L441 = A1L441_p1_out # A1L441_p2_out # A1L441_p3_out;


--~GND~9 is ~GND~9
~GND~9_or_out = GND;
~GND~9 = ~GND~9_or_out;


--~GND~10 is ~GND~10
~GND~10_or_out = GND;
~GND~10 = ~GND~10_or_out;


--~GND~11 is ~GND~11
~GND~11_or_out = GND;
~GND~11 = ~GND~11_or_out;


--~GND~12 is ~GND~12
~GND~12_or_out = GND;
~GND~12 = ~GND~12_or_out;


--~GND~13 is ~GND~13
~GND~13_or_out = GND;
~GND~13 = ~GND~13_or_out;


--~GND~14 is ~GND~14
~GND~14_or_out = GND;
~GND~14 = ~GND~14_or_out;


--~GND~15 is ~GND~15
~GND~15_or_out = GND;
~GND~15 = ~GND~15_or_out;


--~GND~16 is ~GND~16
~GND~16_or_out = GND;
~GND~16 = ~GND~16_or_out;


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~GND~17 is ~GND~17
~GND~17_or_out = GND;
~GND~17 = ~GND~17_or_out;


--A1L74 is reduce_nor~133sexp
A1L74 = EXP(C1_dffs[1] & C1_dffs[0] & !C1_dffs[13] & !C1_dffs[15] & !C1_dffs[12] & C1_dffs[8] & !C1_dffs[3] & !C1_dffs[10] & !C1_dffs[4] & !C1_dffs[5] & !C1_dffs[2] & !C1_dffs[9] & !C1_dffs[6] & !C1_dffs[7] & !C1_dffs[11] & !C1_dffs[14]);


--A1L84 is reduce_nor~136sexp
A1L84 = EXP(!cnt_delay[4] & !cnt_delay[5] & !cnt_delay[0] & !cnt_delay[7] & !cnt_delay[15] & !cnt_delay[17] & !cnt_delay[9] & !cnt_delay[1] & !cnt_delay[6] & !cnt_delay[14] & !cnt_delay[2] & !cnt_delay[16] & !cnt_delay[3] & !cnt_delay[11] & cnt_delay[19] & cnt_delay[10] & cnt_delay[13] & cnt_delay[12] & cnt_delay[8] & cnt_delay[18]);


--A1L94 is reduce_nor~138sexp
A1L94 = EXP(div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1]);


--A1L07 is rtl~4800sexp1
A1L07 = EXP(txd_buf[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[0]);


--A1L17 is rtl~4800sexp2
A1L17 = EXP(txd_buf[1] & div8_tras_reg[2] & div8_tras_reg[0] & div8_tras_reg[1] & !state_tras[3]);


--A1L37 is rtl~4810
A1L37_p1_out = state_tras[1] & !state_tras[3] & key_entry2;
A1L37_p2_out = !state_tras[3] & key_entry2 & state_tras[0];
A1L37 = A1L37_p1_out # A1L37_p2_out;


--A1L811 is trasstart~46bal
A1L811_p1_out = send_state[2] & send_state[0] & send_state[1];
A1L811_or_out = A1L811_p1_out;
A1L811 = !(A1L811_or_out);


--rst is rst
--operation mode is input

rst = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--key_input is key_input
--operation mode is input

key_input = INPUT();


--rxd is rxd
--operation mode is input

rxd = INPUT();


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(~GND~9);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(~GND~10);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(~GND~11);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(~GND~12);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(~GND~13);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(~GND~14);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(~GND~15);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(~GND~16);


--seg_data[0] is seg_data[0]
--operation mode is output

seg_data[0] = OUTPUT(~VCC~1);


--lowbit is lowbit
--operation mode is output

lowbit = OUTPUT(~GND~17);


--seg_data[1] is seg_data[1]
--operation mode is output

seg_data[1] = OUTPUT(A1L25);


--seg_data[4] is seg_data[4]
--operation mode is output

seg_data[4] = OUTPUT(A1L35);


--seg_data[5] is seg_data[5]
--operation mode is output

seg_data[5] = OUTPUT(A1L55);


--seg_data[6] is seg_data[6]
--operation mode is output

seg_data[6] = OUTPUT(A1L75);


--seg_data[7] is seg_data[7]
--operation mode is output

seg_data[7] = OUTPUT(A1L85);


--seg_data[2] is seg_data[2]
--operation mode is output

seg_data[2] = OUTPUT(A1L26);


--seg_data[3] is seg_data[3]
--operation mode is output

seg_data[3] = OUTPUT(A1L56);


--txd is txd
--operation mode is output

txd = OUTPUT(txd_reg);