bcd.tan.qmsg

一些Verilog学习程序B

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[17\] register en\[0\]~reg0 119.85 MHz 8.344 ns Internal " "Info: Clock \"clk\" has Internal fmax of 119.85 MHz between source register \"cnt\[17\]\" and destination register \"en\[0\]~reg0\" (period= 8.344 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.635 ns + Longest register register " "Info: + Longest register to register delay is 7.635 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[17\] 1 REG LC_X6_Y2_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N5; Fanout = 4; REG Node = 'cnt\[17\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[17] } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.373 ns) + CELL(0.511 ns) 1.884 ns Equal0~191 2 COMB LC_X6_Y2_N7 1 " "Info: 2: + IC(1.373 ns) + CELL(0.511 ns) = 1.884 ns; Loc. = LC_X6_Y2_N7; Fanout = 1; COMB Node = 'Equal0~191'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.884 ns" { cnt[17] Equal0~191 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.726 ns) + CELL(0.740 ns) 3.350 ns Equal0~193 3 COMB LC_X6_Y2_N6 1 " "Info: 3: + IC(0.726 ns) + CELL(0.740 ns) = 3.350 ns; Loc. = LC_X6_Y2_N6; Fanout = 1; COMB Node = 'Equal0~193'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.466 ns" { Equal0~191 Equal0~193 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.779 ns) + CELL(0.511 ns) 4.640 ns Equal0~197 4 COMB LC_X6_Y2_N4 4 " "Info: 4: + IC(0.779 ns) + CELL(0.511 ns) = 4.640 ns; Loc. = LC_X6_Y2_N4; Fanout = 4; COMB Node = 'Equal0~197'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.290 ns" { Equal0~193 Equal0~197 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.752 ns) + CELL(1.243 ns) 7.635 ns en\[0\]~reg0 5 REG LC_X5_Y4_N4 4 " "Info: 5: + IC(1.752 ns) + CELL(1.243 ns) = 7.635 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'en\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.995 ns" { Equal0~197 en[0]~reg0 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.005 ns ( 39.36 % ) " "Info: Total cell delay = 3.005 ns ( 39.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.630 ns ( 60.64 % ) " "Info: Total interconnect delay = 4.630 ns ( 60.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.635 ns" { cnt[17] Equal0~191 Equal0~193 Equal0~197 en[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.635 ns" { cnt[17] Equal0~191 Equal0~193 Equal0~197 en[0]~reg0 } { 0.000ns 1.373ns 0.726ns 0.779ns 1.752ns } { 0.000ns 0.511ns 0.740ns 0.511ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns en\[0\]~reg0 2 REG LC_X5_Y4_N4 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N4; Fanout = 4; REG Node = 'en\[0\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk en[0]~reg0 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[0]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[17\] 2 REG LC_X6_Y2_N5 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N5; Fanout = 4; REG Node = 'cnt\[17\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[17] } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[17] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[0]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[17] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.635 ns" { cnt[17] Equal0~191 Equal0~193 Equal0~197 en[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.635 ns" { cnt[17] Equal0~191 Equal0~193 Equal0~197 en[0]~reg0 } { 0.000ns 1.373ns 0.726ns 0.779ns 1.752ns } { 0.000ns 0.511ns 0.740ns 0.511ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[0]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[0]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[17] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c\[7\] en\[1\]~reg0 12.905 ns register " "Info: tco from clock \"clk\" to destination pin \"c\[7\]\" through register \"en\[1\]~reg0\" is 12.905 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 22; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns en\[1\]~reg0 2 REG LC_X5_Y4_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N0; Fanout = 4; REG Node = 'en\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.181 ns + Longest register pin " "Info: + Longest register to pin delay is 9.181 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[1\]~reg0 1 REG LC_X5_Y4_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N0; Fanout = 4; REG Node = 'en\[1\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en[1]~reg0 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.511 ns) 1.508 ns Selector0~24 2 COMB LC_X5_Y4_N6 4 " "Info: 2: + IC(0.997 ns) + CELL(0.511 ns) = 1.508 ns; Loc. = LC_X5_Y4_N6; Fanout = 4; COMB Node = 'Selector0~24'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.508 ns" { en[1]~reg0 Selector0~24 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.157 ns) + CELL(0.200 ns) 2.865 ns Selector0~25 3 COMB LC_X5_Y4_N9 7 " "Info: 3: + IC(1.157 ns) + CELL(0.200 ns) = 2.865 ns; Loc. = LC_X5_Y4_N9; Fanout = 7; COMB Node = 'Selector0~25'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.357 ns" { Selector0~24 Selector0~25 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.914 ns) 5.044 ns WideOr3~15 4 COMB LC_X6_Y4_N6 1 " "Info: 4: + IC(1.265 ns) + CELL(0.914 ns) = 5.044 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'WideOr3~15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.179 ns" { Selector0~25 WideOr3~15 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.815 ns) + CELL(2.322 ns) 9.181 ns c\[7\] 5 PIN PIN_76 0 " "Info: 5: + IC(1.815 ns) + CELL(2.322 ns) = 9.181 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.137 ns" { WideOr3~15 c[7] } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.947 ns ( 42.99 % ) " "Info: Total cell delay = 3.947 ns ( 42.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.234 ns ( 57.01 % ) " "Info: Total interconnect delay = 5.234 ns ( 57.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.181 ns" { en[1]~reg0 Selector0~24 Selector0~25 WideOr3~15 c[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.181 ns" { en[1]~reg0 Selector0~24 Selector0~25 WideOr3~15 c[7] } { 0.000ns 0.997ns 1.157ns 1.265ns 1.815ns } { 0.000ns 0.511ns 0.200ns 0.914ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en[1]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en[1]~reg0 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.181 ns" { en[1]~reg0 Selector0~24 Selector0~25 WideOr3~15 c[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.181 ns" { en[1]~reg0 Selector0~24 Selector0~25 WideOr3~15 c[7] } { 0.000ns 0.997ns 1.157ns 1.265ns 1.815ns } { 0.000ns 0.511ns 0.200ns 0.914ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] c\[7\] 11.399 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"c\[7\]\" is 11.399 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[1\] 1 PIN PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 4; PIN Node = 'a\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.814 ns) + CELL(0.511 ns) 4.457 ns Selector3~100 2 COMB LC_X5_Y4_N2 1 " "Info: 2: + IC(2.814 ns) + CELL(0.511 ns) = 4.457 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'Selector3~100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.325 ns" { a[1] Selector3~100 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.200 ns) 5.385 ns Selector3~101 3 COMB LC_X5_Y4_N1 7 " "Info: 3: + IC(0.728 ns) + CELL(0.200 ns) = 5.385 ns; Loc. = LC_X5_Y4_N1; Fanout = 7; COMB Node = 'Selector3~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.928 ns" { Selector3~100 Selector3~101 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.511 ns) 7.262 ns WideOr3~15 4 COMB LC_X6_Y4_N6 1 " "Info: 4: + IC(1.366 ns) + CELL(0.511 ns) = 7.262 ns; Loc. = LC_X6_Y4_N6; Fanout = 1; COMB Node = 'WideOr3~15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.877 ns" { Selector3~101 WideOr3~15 } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.815 ns) + CELL(2.322 ns) 11.399 ns c\[7\] 5 PIN PIN_76 0 " "Info: 5: + IC(1.815 ns) + CELL(2.322 ns) = 11.399 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.137 ns" { WideOr3~15 c[7] } "NODE_NAME" } } { "bcd.v" "" { Text "E:/Verilog/基础实验/二进制转BCD码/bcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.676 ns ( 41.02 % ) " "Info: Total cell delay = 4.676 ns ( 41.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.723 ns ( 58.98 % ) " "Info: Total interconnect delay = 6.723 ns ( 58.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.399 ns" { a[1] Selector3~100 Selector3~101 WideOr3~15 c[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.399 ns" { a[1] a[1]~combout Selector3~100 Selector3~101 WideOr3~15 c[7] } { 0.000ns 0.000ns 2.814ns 0.728ns 1.366ns 1.815ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.511ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:24:31 2009 " "Info: Processing ended: Sun Jan 11 21:24:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}