state_machine.map.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 21:39:07 2009 " "Info: Processing started: Sun Jan 11 21:39:07 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off state_machine -c state_machine" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "state_machine.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file state_machine.v" { { "Info" "ISGN_ENTITY_NAME" "1 state_machine " "Info: Found entity 1: state_machine" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "state_machine " "Info: Elaborating entity \"state_machine\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 state_machine.v(34) " "Warning (10230): Verilog HDL assignment warning at state_machine.v(34): truncated value with size 32 to match size of target (24)" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|state_machine\|state 8 " "Info: State machine \"\|state_machine\|state\" contains 8 states" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|state_machine\|state " "Info: Selected Auto state machine encoding method for state machine \"\|state_machine\|state\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|state_machine\|state " "Info: Encoding result for state machine \"\|state_machine\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state7 " "Info: Encoded state bit \"state.state7\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state1 " "Info: Encoded state bit \"state.state1\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state2 " "Info: Encoded state bit \"state.state2\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state3 " "Info: Encoded state bit \"state.state3\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state4 " "Info: Encoded state bit \"state.state4\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state5 " "Info: Encoded state bit \"state.state5\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state6 " "Info: Encoded state bit \"state.state6\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.state0 " "Info: Encoded state bit \"state.state0\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state0 00000000 " "Info: State \"\|state_machine\|state.state0\" uses code string \"00000000\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state6 00000011 " "Info: State \"\|state_machine\|state.state6\" uses code string \"00000011\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state5 00000101 " "Info: State \"\|state_machine\|state.state5\" uses code string \"00000101\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state4 00001001 " "Info: State \"\|state_machine\|state.state4\" uses code string \"00001001\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state3 00010001 " "Info: State \"\|state_machine\|state.state3\" uses code string \"00010001\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state2 00100001 " "Info: State \"\|state_machine\|state.state2\" uses code string \"00100001\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state1 01000001 " "Info: State \"\|state_machine\|state.state1\" uses code string \"01000001\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|state_machine\|state.state7 10000001 " "Info: State \"\|state_machine\|state.state7\" uses code string \"10000001\"" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 21 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning: Pin \"c\[0\]\" stuck at VCC" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning: Pin \"en\[0\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] GND " "Warning: Pin \"en\[1\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] GND " "Warning: Pin \"en\[2\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] GND " "Warning: Pin \"en\[3\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] GND " "Warning: Pin \"en\[4\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] GND " "Warning: Pin \"en\[5\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] GND " "Warning: Pin \"en\[6\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] GND " "Warning: Pin \"en\[7\]\" stuck at GND" {  } { { "state_machine.v" "" { Text "E:/Verilog/基础实验/简单状态机/state_machine.v" 10 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "64 " "Info: Implemented 64 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:39:09 2009 " "Info: Processing ended: Sun Jan 11 21:39:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}