state_machine.tan.rpt

一些Verilog学习程序B

; N/A                                     ; 162.81 MHz ( period = 6.142 ns )                    ; cnt[0]  ; state.state4 ; clk        ; clk      ; None                        ; None                      ; 5.433 ns                ;
; N/A                                     ; 162.81 MHz ( period = 6.142 ns )                    ; cnt[0]  ; state.state2 ; clk        ; clk      ; None                        ; None                      ; 5.433 ns                ;
; N/A                                     ; 167.22 MHz ( period = 5.980 ns )                    ; cnt[18] ; state.state1 ; clk        ; clk      ; None                        ; None                      ; 5.271 ns                ;
; N/A                                     ; 167.22 MHz ( period = 5.980 ns )                    ; cnt[18] ; state.state0 ; clk        ; clk      ; None                        ; None                      ; 5.271 ns                ;
; N/A                                     ; 167.22 MHz ( period = 5.980 ns )                    ; cnt[18] ; state.state3 ; clk        ; clk      ; None                        ; None                      ; 5.271 ns                ;
; N/A                                     ; 174.86 MHz ( period = 5.719 ns )                    ; cnt[0]  ; state.state1 ; clk        ; clk      ; None                        ; None                      ; 5.010 ns                ;
; N/A                                     ; 174.86 MHz ( period = 5.719 ns )                    ; cnt[0]  ; state.state0 ; clk        ; clk      ; None                        ; None                      ; 5.010 ns                ;
; N/A                                     ; 174.86 MHz ( period = 5.719 ns )                    ; cnt[0]  ; state.state3 ; clk        ; clk      ; None                        ; None                      ; 5.010 ns                ;
; N/A                                     ; 179.02 MHz ( period = 5.586 ns )                    ; cnt[0]  ; cnt[10]      ; clk        ; clk      ; None                        ; None                      ; 4.877 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+--------------+------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To   ; From Clock ;
+-------+--------------+------------+--------------+------+------------+
; N/A   ; None         ; 9.336 ns   ; state.state4 ; c[7] ; clk        ;
; N/A   ; None         ; 8.860 ns   ; state.state6 ; c[6] ; clk        ;
; N/A   ; None         ; 8.758 ns   ; state.state0 ; c[2] ; clk        ;
; N/A   ; None         ; 8.745 ns   ; state.state0 ; c[1] ; clk        ;
; N/A   ; None         ; 8.679 ns   ; state.state1 ; c[7] ; clk        ;
; N/A   ; None         ; 8.511 ns   ; state.state2 ; c[5] ; clk        ;
; N/A   ; None         ; 8.490 ns   ; state.state5 ; c[2] ; clk        ;
; N/A   ; None         ; 8.334 ns   ; state.state5 ; c[6] ; clk        ;
; N/A   ; None         ; 8.317 ns   ; state.state7 ; c[4] ; clk        ;
; N/A   ; None         ; 8.317 ns   ; state.state6 ; c[3] ; clk        ;
; N/A   ; None         ; 8.209 ns   ; state.state0 ; c[3] ; clk        ;
; N/A   ; None         ; 8.189 ns   ; state.state1 ; c[4] ; clk        ;
; N/A   ; None         ; 8.177 ns   ; state.state1 ; c[1] ; clk        ;
; N/A   ; None         ; 7.767 ns   ; state.state4 ; c[2] ; clk        ;
; N/A   ; None         ; 7.267 ns   ; state.state4 ; c[4] ; clk        ;
; N/A   ; None         ; 7.267 ns   ; state.state6 ; c[2] ; clk        ;
; N/A   ; None         ; 7.260 ns   ; state.state2 ; c[3] ; clk        ;
; N/A   ; None         ; 7.253 ns   ; state.state7 ; c[1] ; clk        ;
+-------+--------------+------------+--------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jan 11 21:39:28 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_machine -c state_machine
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 123.43 MHz between source register "cnt[11]" and destination register "state.state7" (period= 8.102 ns)
    Info: + Longest register to register delay is 7.393 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'cnt[11]'
        Info: 2: + IC(2.887 ns) + CELL(0.200 ns) = 3.087 ns; Loc. = LC_X5_Y4_N2; Fanout = 1; COMB Node = 'Equal0~242'
        Info: 3: + IC(0.732 ns) + CELL(0.740 ns) = 4.559 ns; Loc. = LC_X5_Y4_N5; Fanout = 1; COMB Node = 'Equal0~244'
        Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.064 ns; Loc. = LC_X5_Y4_N6; Fanout = 8; COMB Node = 'Equal0~247'
        Info: 5: + IC(1.086 ns) + CELL(1.243 ns) = 7.393 ns; Loc. = LC_X6_Y4_N0; Fanout = 3; REG Node = 'state.state7'
        Info: Total cell delay = 2.383 ns ( 32.23 % )
        Info: Total interconnect delay = 5.010 ns ( 67.77 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N0; Fanout = 3; REG Node = 'state.state7'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'cnt[11]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "c[7]" through register "state.state4" is 9.336 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N3; Fanout = 4; REG Node = 'state.state4'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.612 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N3; Fanout = 4; REG Node = 'state.state4'
        Info: 2: + IC(1.910 ns) + CELL(0.740 ns) = 2.650 ns; Loc. = LC_X7_Y4_N2; Fanout = 1; COMB Node = 'c~9'
        Info: 3: + IC(0.640 ns) + CELL(2.322 ns) = 5.612 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c[7]'
        Info: Total cell delay = 3.062 ns ( 54.56 % )
        Info: Total interconnect delay = 2.550 ns ( 45.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Jan 11 21:39:29 2009
    Info: Elapsed time: 00:00:03