encode.tan.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 20:43:49 2009 " "Info: Processing started: Sun Jan 11 20:43:49 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[2\] c\[7\] 10.788 ns Longest " "Info: Longest tpd from source pin \"a\[2\]\" to destination pin \"c\[7\]\" is 10.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[2\] 1 PIN PIN_28 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 4; PIN Node = 'a\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "encode.v" "" { Text "E:/Verilog/基础实验/8位优先编码器/encode.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.990 ns) + CELL(0.740 ns) 3.862 ns c_tmp~143 2 COMB LC_X3_Y1_N6 1 " "Info: 2: + IC(1.990 ns) + CELL(0.740 ns) = 3.862 ns; Loc. = LC_X3_Y1_N6; Fanout = 1; COMB Node = 'c_tmp~143'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.730 ns" { a[2] c_tmp~143 } "NODE_NAME" } } { "encode.v" "" { Text "E:/Verilog/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.367 ns c_tmp~144 3 COMB LC_X3_Y1_N7 4 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.367 ns; Loc. = LC_X3_Y1_N7; Fanout = 4; COMB Node = 'c_tmp~144'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { c_tmp~143 c_tmp~144 } "NODE_NAME" } } { "encode.v" "" { Text "E:/Verilog/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.803 ns) + CELL(0.740 ns) 5.910 ns WideOr0~4 4 COMB LC_X3_Y1_N1 1 " "Info: 4: + IC(0.803 ns) + CELL(0.740 ns) = 5.910 ns; Loc. = LC_X3_Y1_N1; Fanout = 1; COMB Node = 'WideOr0~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.543 ns" { c_tmp~144 WideOr0~4 } "NODE_NAME" } } { "encode.v" "" { Text "E:/Verilog/基础实验/8位优先编码器/encode.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.556 ns) + CELL(2.322 ns) 10.788 ns c\[7\] 5 PIN PIN_76 0 " "Info: 5: + IC(2.556 ns) + CELL(2.322 ns) = 10.788 ns; Loc. = PIN_76; Fanout = 0; PIN Node = 'c\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.878 ns" { WideOr0~4 c[7] } "NODE_NAME" } } { "encode.v" "" { Text "E:/Verilog/基础实验/8位优先编码器/encode.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.134 ns ( 47.59 % ) " "Info: Total cell delay = 5.134 ns ( 47.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.654 ns ( 52.41 % ) " "Info: Total interconnect delay = 5.654 ns ( 52.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.788 ns" { a[2] c_tmp~143 c_tmp~144 WideOr0~4 c[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.788 ns" { a[2] a[2]~combout c_tmp~143 c_tmp~144 WideOr0~4 c[7] } { 0.000ns 0.000ns 1.990ns 0.305ns 0.803ns 2.556ns } { 0.000ns 1.132ns 0.740ns 0.200ns 0.740ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 20:43:50 2009 " "Info: Processing ended: Sun Jan 11 20:43:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}