sub.map.eqn

一些Verilog学习程序B

A1L06_p1_out = b[2] & !b[1] & !b[3] & a[3];
A1L06_p2_out = !b[2] & b[1] & !b[3] & a[3] & !a[1];
A1L06_p3_out = b[2] & !b[1] & b[3] & !a[3];
A1L06_p4_out = !b[2] & b[1] & b[3] & !a[3] & !a[1];
A1L06_or_out = A1L06_p0_out # A1L06_p1_out # A1L06_p2_out # A1L06_p3_out # A1L06_p4_out;
A1L06 = A1L06_or_out;


--A1L36 is reduce_or~1303
A1L36_p1_out = A1L16 & A1L26 & !A1L65 & !A1L75 & !A1L85 & !A1L95 & !A1L06 & A1L55;
A1L36_or_out = A1L36_p1_out;
A1L36 = A1L36_or_out;


--E3L4 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~46
E3L4_p0_out = !b[0] & a[1] & !b[2] & a[2] & b[1];
E3L4_p1_out = !b[0] & !a[1] & !b[2] & !a[2];
E3L4_p2_out = !a[1] & !b[2] & !a[2] & a[0];
E3L4_p3_out = !b[0] & !a[1] & b[2] & a[2];
E3L4_p4_out = !a[1] & b[2] & a[2] & a[0];
E3L4 = E3L4_p0_out # E3L4_p1_out # E3L4_p2_out # E3L4_p3_out # E3L4_p4_out;


--E3L5 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~52
E3L5_p0_out = b[0] & !b[2] & !a[2] & b[1] & !a[0];
E3L5_p1_out = !b[0] & a[1] & b[2] & !a[2] & b[1];
E3L5_p2_out = a[1] & !b[2] & a[2] & b[1] & a[0];
E3L5_p3_out = a[1] & b[2] & !a[2] & b[1] & a[0];
E3L5_p4_out = b[0] & b[2] & a[2] & b[1] & !a[0];
E3L5 = E3L4 # E3L5_p0_out # E3L5_p1_out # E3L5_p2_out # E3L5_p3_out # E3L5_p4_out;


--E3L9 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~58
E3L9_p1_out = !a[2] & b[1] & b[0] & !a[0];
E3L9_p2_out = !a[2] & b[1] & !a[1];
E3L9_p3_out = !a[2] & b[2];
E3L9 = E3L9_p1_out # E3L9_p2_out # E3L9_p3_out;


--A1L46 is reduce_or~1305
A1L46_p0_out = !a[3] & b[3] & !a[1] & !a[2] & !b[0] & a[0];
A1L46_p1_out = !a[3] & !b[3] & !a[1] & !b[1] & a[2] & !b[2];
A1L46_p2_out = !a[3] & b[3] & !a[1] & !b[1] & !a[2] & b[2];
A1L46_p3_out = a[3] & !b[3] & !a[1] & !b[1] & !a[2] & b[2];
A1L46_p4_out = a[3] & !b[3] & !a[1] & !a[2] & !b[0] & a[0];
A1L46 = A1L46_p0_out # A1L46_p1_out # A1L46_p2_out # A1L46_p3_out # A1L46_p4_out;


--A1L56 is reduce_or~1311
A1L56_p0_out = !a[3] & b[3] & a[1] & b[1] & !a[2] & b[2];
A1L56_p1_out = a[3] & b[3] & !a[1] & !b[1] & a[2] & !b[2];
A1L56_p2_out = !a[3] & !b[3] & a[1] & b[1] & a[2] & !b[2];
A1L56_p3_out = !a[3] & b[3] & !a[1] & b[2] & !b[0] & a[0];
A1L56_p4_out = a[3] & !b[3] & !a[1] & b[2] & !b[0] & a[0];
A1L56 = A1L46 # A1L56_p0_out # A1L56_p1_out # A1L56_p2_out # A1L56_p3_out # A1L56_p4_out;


--A1L66 is reduce_or~1317
A1L66_p0_out = !a[3] & !b[3] & !b[0] & a[2] & a[0] & !b[1];
A1L66_p1_out = !a[3] & b[3] & b[0] & !a[2] & !a[0];
A1L66_p2_out = a[3] & !b[3] & b[0] & !a[2] & !a[0];
A1L66_p3_out = a[3] & !b[3] & b[0] & !a[0] & b[2];
A1L66_p4_out = !a[3] & b[3] & b[0] & !a[0] & b[2];
A1L66 = A1L66_p0_out # A1L66_p1_out # A1L66_p2_out # A1L66_p3_out # A1L66_p4_out;


--A1L76 is reduce_or~1323
A1L76_p0_out = !b[0] & b[1] & b[2] & a[0] & a[2] & a[1];
A1L76_p1_out = a[3] & b[3] & !b[0] & !b[1] & !b[2] & a[0];
A1L76_p2_out = !a[3] & !b[3] & !b[0] & !b[1] & !b[2] & a[0];
A1L76_p3_out = a[3] & b[3] & !b[0] & !b[2] & a[0] & a[2];
A1L76_p4_out = !a[3] & !b[3] & !b[0] & !b[2] & a[0] & a[2];
A1L76 = A1L66 # A1L76_p0_out # A1L76_p1_out # A1L76_p2_out # A1L76_p3_out # A1L76_p4_out;


--A1L86 is reduce_or~1329
A1L86_p0_out = b[0] & !a[1] & !b[1] & !a[3] & !b[3] & !a[0];
A1L86_p1_out = !b[0] & !a[1] & b[1] & !a[3] & !b[3];
A1L86_p2_out = a[1] & !b[1] & a[3] & !b[3] & !a[0];
A1L86_p3_out = a[1] & !b[1] & !a[3] & b[3] & !a[0];
A1L86_p4_out = !b[0] & !a[1] & b[1] & a[3] & b[3];
A1L86 = A1L86_p0_out # A1L86_p1_out # A1L86_p2_out # A1L86_p3_out # A1L86_p4_out;


--A1L96 is reduce_or~1335
A1L96_p0_out = !a[1] & !b[1] & a[3] & !b[3] & !b[0] & b[2];
A1L96_p1_out = !a[1] & b[1] & !a[2] & !a[3] & !b[3];
A1L96_p2_out = !a[1] & b[1] & !a[2] & a[3] & b[3];
A1L96_p3_out = !a[1] & !b[1] & !a[2] & a[3] & !b[3] & !b[0];
A1L96_p4_out = !a[1] & !b[1] & !a[3] & b[3] & !b[0] & b[2];
A1L96 = A1L96_p0_out # A1L96_p1_out # A1L96_p2_out # A1L96_p3_out # A1L96_p4_out;


--A1L07 is reduce_or~1341
A1L07_p0_out = b[0] & a[0] & !a[2] & !a[3] & b[3];
A1L07_p1_out = !b[0] & !a[0] & !a[2] & !a[3] & b[3];
A1L07_p2_out = !b[0] & !a[0] & !a[2] & a[3] & !b[3];
A1L07_p3_out = !b[0] & !a[0] & !a[3] & b[3] & b[2];
A1L07_p4_out = !b[0] & !a[0] & a[3] & !b[3] & b[2];
A1L07 = A1L07_p0_out # A1L07_p1_out # A1L07_p2_out # A1L07_p3_out # A1L07_p4_out;


--A1L17 is reduce_or~1347
A1L17_p0_out = b[0] & a[0] & b[2] & !a[3] & b[3];
A1L17_p1_out = b[0] & a[0] & a[1] & !b[1];
A1L17_p2_out = b[0] & a[0] & !a[1] & b[1];
A1L17_p3_out = !b[0] & !a[0] & a[1] & !b[1];
A1L17_p4_out = !b[0] & !a[0] & !a[1] & b[1];
A1L17 = A1L17_p0_out # A1L17_p1_out # A1L17_p2_out # A1L17_p3_out # A1L17_p4_out;


--A1L27 is reduce_or~1353
A1L27_p0_out = a[0] & !a[1] & a[2] & !b[2] & !b[0];
A1L27_p1_out = !a[0] & !a[1] & b[1] & !a[2] & !b[2];
A1L27_p2_out = !a[0] & !a[1] & b[1] & a[2] & b[2];
A1L27_p3_out = a[0] & b[1] & a[2] & !b[2] & !b[0];
A1L27_p4_out = a[0] & b[1] & !a[2] & b[2] & !b[0];
A1L27 = A1L27_p0_out # A1L27_p1_out # A1L27_p2_out # A1L27_p3_out # A1L27_p4_out;


--A1L37 is reduce_or~1359
A1L37_p0_out = a[0] & !b[1] & !a[1] & a[2] & !b[2] & a[3] & b[3] & b[0];
A1L37_p1_out = a[0] & b[1] & a[1] & a[2] & !b[2] & a[3] & b[3] & b[0];
A1L37_p2_out = a[0] & b[1] & a[1] & a[2] & !b[2] & !a[3] & !b[3] & b[0];
A1L37_p3_out = a[0] & b[1] & a[1] & !a[2] & b[2] & a[3] & !b[3] & b[0];
A1L37_p4_out = a[0] & b[1] & a[1] & !a[2] & b[2] & !a[3] & b[3] & b[0];
A1L37 = A1L37_p0_out # A1L37_p1_out # A1L37_p2_out # A1L37_p3_out # A1L37_p4_out;


--A1L47 is reduce_or~1365
A1L47_p0_out = !a[0] & !b[1] & !a[1] & !a[2] & b[2] & a[3] & !b[3] & !b[0];
A1L47_p1_out = !a[0] & b[1] & a[1] & !a[2] & b[2] & a[3] & !b[3] & !b[0];
A1L47_p2_out = !a[0] & b[1] & a[1] & !a[2] & b[2] & !a[3] & b[3] & !b[0];
A1L47_p3_out = !a[0] & !b[1] & !a[1] & a[2] & !b[2] & a[3] & b[3] & !b[0];
A1L47_p4_out = !a[0] & !b[1] & !a[1] & a[2] & !b[2] & !a[3] & !b[3] & !b[0];
A1L47 = A1L47_p0_out # A1L47_p1_out # A1L47_p2_out # A1L47_p3_out # A1L47_p4_out;


--A1L57 is reduce_or~1371
A1L57_p0_out = !a[0] & !b[1] & a[1] & a[2] & b[2] & a[3] & !b[3];
A1L57_p1_out = !a[0] & b[1] & !a[1] & !a[2] & b[2] & a[3] & b[3];
A1L57_p2_out = b[1] & !a[1] & !a[2] & b[2] & a[3] & b[3] & b[0];
A1L57_p3_out = !a[0] & b[1] & !a[1] & !a[2] & b[2] & !a[3] & !b[3];
A1L57_p4_out = b[1] & !a[1] & !a[2] & b[2] & !a[3] & !b[3] & b[0];
A1L57 = A1L57_p0_out # A1L57_p1_out # A1L57_p2_out # A1L57_p3_out # A1L57_p4_out;


--A1L67 is reduce_or~1377
A1L67_p0_out = !a[0] & b[1] & !a[2] & b[2] & b[0] & !a[1];
A1L67_p1_out = !a[0] & !b[1] & !a[2] & !b[2] & b[0];
A1L67_p2_out = !a[0] & !a[2] & !b[2] & b[0] & a[1];
A1L67_p3_out = !a[0] & !b[1] & a[2] & b[2] & b[0];
A1L67_p4_out = !a[0] & a[2] & b[2] & b[0] & a[1];
A1L67 = A1L67_p0_out # A1L67_p1_out # A1L67_p2_out # A1L67_p3_out # A1L67_p4_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--A1L22 is reduce_or~1120sexp3
A1L22 = EXP(b[0] & !b[1] & a[2] & !b[2] & !a[0] & !a[3] & b[3] & a[1]);


--A1L32 is reduce_or~1120sexp4
A1L32 = EXP(!b[0] & !b[1] & !a[2] & b[2] & a[0] & a[3] & !b[3] & a[1]);


--A1L42 is reduce_or~1120sexp5
A1L42 = EXP(!b[0] & !b[1] & !a[2] & b[2] & a[0] & !a[3] & b[3] & a[1]);


--A1L55 is reduce_or~1266sexp5
A1L55 = EXP(!b[2] & !b[1] & a[2] & b[3] & a[3]);


--A1L23 is reduce_or~1163bal
A1L23_p0_out = b[1] & a[2] & !b[2] & !a[3] & b[3] & a[1] & !b[0] & a[0];
A1L23_p1_out = b[1] & !a[2] & b[2] & a[3] & !b[3] & !a[1];
A1L23_p2_out = b[1] & a[2] & !b[2] & a[3] & b[3] & !a[1];
A1L23_p3_out = !b[1] & a[2] & b[2] & a[3] & b[3] & a[1];
A1L23_p4_out = b[1] & a[2] & !b[2] & a[3] & !b[3] & a[1] & !b[0] & a[0];
A1L23_or_out = A1L23_p0_out # A1L23_p1_out # A1L23_p2_out # A1L23_p3_out # A1L23_p4_out;
A1L23 = !(A1L23_or_out);


--A1L26 is reduce_or~1302bal
A1L26_p0_out = !b[3] & !a[3] & !b[2] & a[1] & a[2];
A1L26_p1_out = !b[3] & a[3] & !a[0] & b[0];
A1L26_p2_out = !b[3] & !a[3] & b[2] & b[1] & !a[1] & !a[2];
A1L26_p3_out = b[3] & a[3] & b[2] & b[1] & !a[1] & !a[2];
A1L26_p4_out = !b[3] & !a[3] & !b[2] & !b[1] & a[2];
A1L26_or_out = A1L26_p0_out # A1L26_p1_out # A1L26_p2_out # A1L26_p3_out # A1L26_p4_out;
A1L26 = !(A1L26_or_out);


--A1L16 is reduce_or~1297bal
A1L16_p0_out = b[3] & !a[3] & !a[0] & b[0];
A1L16_p1_out = !b[2] & !a[2] & b[3] & !a[3];
A1L16_p2_out = b[1] & !a[1] & !a[0] & b[0];
A1L16_p3_out = !b[1] & a[1] & !a[0] & b[0];
A1L16_p4_out = b[2] & !a[2] & !a[0] & b[0];
A1L16_or_out = A1L16_p0_out # A1L16_p1_out # A1L16_p2_out # A1L16_p3_out # A1L16_p4_out;
A1L16 = !(A1L16_or_out);


--A1L12 is reduce_or~1114sexp3bal
A1L12_p0_out = !b[0] & a[2] & b[2] & a[0] & !a[3] & !b[3] & a[1];
A1L12_p1_out = !b[0] & !b[1] & a[2] & !b[2] & a[0] & a[3] & !b[3] & !a[1];
A1L12_p2_out = !b[0] & !b[1] & a[2] & !b[2] & a[0] & !a[3] & b[3] & !a[1];
A1L12_p3_out = b[0] & !b[1] & a[2] & !b[2] & !a[0] & a[3] & !b[3] & a[1];
A1L12_p4_out = !b[0] & !b[1] & a[2] & b[2] & a[0] & !a[3] & !b[3];
A1L12_or_out = A1L12_p0_out # A1L12_p1_out # A1L12_p2_out # A1L12_p3_out # A1L12_p4_out;
A1L12 = !(A1L12_or_out);


--A1L25 is reduce_or~1249bal
A1L25_p1_out = a[0] & b[1] & a[2] & b[2] & !b[0];
A1L25_p2_out = a[0] & b[1] & !a[2] & !b[2] & !b[0];
A1L25_p3_out = a[0] & a[2] & b[2] & !b[0] & !a[1];
A1L25_p4_out = a[0] & !a[2] & !b[2] & !b[0] & !a[1];
A1L25_or_out = A1L25_p1_out # A1L25_p2_out # A1L25_p3_out # A1L25_p4_out;
A1L25 = !(A1L25_or_out);


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en is en
--operation mode is output

en = OUTPUT(~GND~0);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L33);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L14);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L43);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(A1L74);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L35);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(A1L45);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L36);