sub.map.eqn

一些Verilog学习程序B

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--E3L1 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[1]~24
E3L1_p1_out = b[0] & a[0];
E3L1_p2_out = !b[0] & !a[0];
E3L1_or_out = E3L1_p1_out # E3L1_p2_out;
E3L1 = E3L1_or_out;


--E3L2 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[2]~25
E3L2_p1_out = b[0] & !a[0];
E3L2_p2_out = b[1] & a[1];
E3L2_p3_out = !b[1] & !a[1];
E3L2_or_out = E3L2_p2_out # E3L2_p3_out;
E3L2 = E3L2_p1_out $ E3L2_or_out;


--E3L3 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~30
E3L3_p0_out = a[1] & b[2] & a[2] & !b[1];
E3L3_p2_out = b[0] & !a[1] & b[2] & !a[2] & !b[1] & !a[0];
E3L3_p3_out = b[0] & !a[1] & !b[2] & a[2] & !b[1] & !a[0];
E3L3_p4_out = a[1] & !b[2] & !a[2] & !b[1];
E3L3_or_out = E3L5 # E3L3_p0_out # E3L3_p2_out # E3L3_p3_out # E3L3_p4_out;
E3L3 = !b[1] $ E3L3_or_out;


--E3L6 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37
E3L6 = EXP(b[3] & a[3]);


--E3L7 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~38
E3L7 = EXP(!a[3] & !b[3]);


--E3L8 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39
E3L8_p1_out = E3L6 & E3L7;
E3L8_p0_out = b[0] & !a[1] & !a[0] & b[2];
E3L8_p2_out = !a[2] & b[0] & !a[1] & !a[0];
E3L8_p3_out = b[0] & !a[0] & b[1] & b[2];
E3L8_p4_out = !a[1] & b[1] & b[2];
E3L8_or_out = E3L9 # E3L8_p0_out # E3L8_p2_out # E3L8_p3_out # E3L8_p4_out;
E3L8 = E3L8_p1_out $ E3L8_or_out;


--A1L52 is reduce_or~1126
A1L52_p0_out = b[0] & b[1] & a[2] & !b[2] & !a[0] & !a[3] & !b[3];
A1L52_p1_out = !b[0] & !b[1] & a[2] & b[2] & a[0] & a[3] & b[3];
A1L52_p2_out = !b[0] & b[1] & !a[2] & a[0] & a[3] & b[3] & a[1];
A1L52_p3_out = !b[0] & b[1] & !a[2] & a[0] & !a[3] & !b[3] & a[1];
A1L52_p4_out = b[0] & b[1] & a[2] & !b[2] & !a[0] & a[3] & b[3];
A1L52_or_out = A1L52_p0_out # A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = A1L52_or_out;


--A1L62 is reduce_or~1132
A1L62_p0_out = b[0] & b[1] & a[2] & !a[0] & a[3] & b[3] & !a[1];
A1L62_p1_out = !b[0] & !b[1] & !a[2] & a[0] & a[3] & b[3] & !a[1];
A1L62_p2_out = !b[0] & !b[1] & !a[2] & a[0] & !a[3] & !b[3] & !a[1];
A1L62_p3_out = b[0] & !b[1] & !a[2] & !a[0] & a[3] & b[3] & a[1];
A1L62_p4_out = b[0] & !b[1] & !a[2] & !a[0] & !a[3] & !b[3] & a[1];
A1L62_or_out = A1L62_p0_out # A1L62_p1_out # A1L62_p2_out # A1L62_p3_out # A1L62_p4_out;
A1L62 = A1L62_or_out;


--A1L72 is reduce_or~1138
A1L72_p0_out = b[0] & a[2] & !b[2] & !a[0] & !a[3] & !b[3] & !a[1];
A1L72_p1_out = !b[0] & a[2] & b[2] & a[0] & a[3] & b[3] & a[1];
A1L72_p2_out = b[0] & a[2] & !a[0] & !a[3] & !b[3] & !a[1] & b[1];
A1L72_p3_out = b[0] & !b[2] & !a[0] & a[3] & b[3] & !a[1] & b[1];
A1L72_p4_out = b[0] & a[2] & !b[2] & !a[0] & a[3] & b[3] & !a[1];
A1L72_or_out = A1L72_p0_out # A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = A1L72_or_out;


--A1L82 is reduce_or~1144
A1L82_p0_out = !b[0] & b[1] & b[2] & a[0] & !a[3] & b[3] & !a[1];
A1L82_p1_out = b[0] & b[1] & !b[2] & !a[0] & !a[3] & !b[3] & !a[1];
A1L82_p2_out = !b[0] & !b[1] & !b[2] & a[0] & a[3] & b[3] & a[1];
A1L82_p3_out = !b[0] & !b[1] & !b[2] & a[0] & !a[3] & !b[3] & a[1];
A1L82_p4_out = !b[0] & b[1] & b[2] & a[0] & a[3] & !b[3] & !a[1];
A1L82_or_out = A1L82_p0_out # A1L82_p1_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;
A1L82 = A1L82_or_out;


--A1L92 is reduce_or~1150
A1L92_p0_out = b[0] & !b[1] & !a[2] & !a[0] & a[3] & !b[3] & !a[1];
A1L92_p1_out = !b[0] & b[1] & !a[2] & a[0] & a[3] & !b[3] & !a[1];
A1L92_p2_out = !b[0] & b[1] & !a[2] & a[0] & !a[3] & b[3] & !a[1];
A1L92_p3_out = b[0] & b[1] & !a[2] & !a[0] & a[3] & !b[3] & a[1];
A1L92_p4_out = b[0] & b[1] & !a[2] & !a[0] & !a[3] & b[3] & a[1];
A1L92_or_out = A1L92_p0_out # A1L92_p1_out # A1L92_p2_out # A1L92_p3_out # A1L92_p4_out;
A1L92 = A1L92_or_out;


--A1L03 is reduce_or~1156
A1L03_p0_out = b[0] & !b[1] & !a[0] & !a[3] & b[3] & !a[1] & !a[2];
A1L03_p1_out = b[0] & b[1] & b[2] & !a[0] & a[3] & !b[3] & a[1];
A1L03_p2_out = b[0] & b[1] & b[2] & !a[0] & !a[3] & b[3] & a[1];
A1L03_p3_out = b[0] & !b[1] & b[2] & !a[0] & a[3] & !b[3] & !a[1];
A1L03_p4_out = b[0] & !b[1] & b[2] & !a[0] & !a[3] & b[3] & !a[1];
A1L03_or_out = A1L03_p0_out # A1L03_p1_out # A1L03_p2_out # A1L03_p3_out # A1L03_p4_out;
A1L03 = A1L03_or_out;


--A1L13 is reduce_or~1162
A1L13_p0_out = b[1] & !a[2] & b[2] & !a[3] & b[3] & !a[1];
A1L13_p1_out = !b[1] & !a[2] & !b[2] & !a[3] & !b[3] & a[1];
A1L13_p2_out = b[1] & a[2] & !b[2] & !a[3] & !b[3] & !a[1];
A1L13_p3_out = !b[1] & !a[2] & !b[2] & a[3] & b[3] & a[1];
A1L13_p4_out = !b[1] & a[2] & b[2] & !a[3] & !b[3] & a[1];
A1L13_or_out = A1L13_p0_out # A1L13_p1_out # A1L13_p2_out # A1L13_p3_out # A1L13_p4_out;
A1L13 = A1L13_or_out;


--A1L33 is reduce_or~1166
A1L33_p1_out = A1L23 & !A1L52 & !A1L62 & !A1L72 & !A1L82 & !A1L92 & !A1L03 & !A1L13 & A1L12 & A1L22 & A1L32 & A1L42;
A1L33_or_out = A1L33_p1_out;
A1L33 = !(A1L33_or_out);


--A1L43 is reduce_or~1173
A1L43_p1_out = E3L1 & !E3L8 & E3L2 & E3L3;
A1L43_p2_out = !E3L1 & !E3L8 & E3L2 & !E3L3;
A1L43_p3_out = !E3L1 & E3L8 & E3L2 & E3L3;
A1L43_p4_out = !E3L1 & E3L8 & !E3L2 & !E3L3;
A1L43_or_out = A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--A1L53 is reduce_or~1179
A1L53_p0_out = a[3] & b[3] & !b[1] & a[2] & !b[0] & a[0];
A1L53_p1_out = a[3] & !b[3] & a[1] & b[1] & !a[2] & b[2];
A1L53_p2_out = a[3] & b[3] & a[1] & b[1] & a[2] & !b[2];
A1L53_p3_out = a[3] & !b[3] & !a[2] & b[2] & !b[0] & a[0];
A1L53_p4_out = !a[3] & b[3] & !a[2] & b[2] & !b[0] & a[0];
A1L53_or_out = A1L56 # A1L53_p0_out # A1L53_p1_out # A1L53_p2_out # A1L53_p3_out # A1L53_p4_out;
A1L53 = A1L53_or_out;


--A1L63 is reduce_or~1185
A1L63_p0_out = b[0] & a[2] & !b[2] & !a[0] & !a[3] & !b[3];
A1L63_p1_out = !b[0] & a[1] & b[1] & !a[2] & !b[2] & a[0];
A1L63_p2_out = !b[0] & !a[1] & !b[1] & a[2] & b[2] & a[0];
A1L63_p3_out = !b[0] & !a[1] & !b[1] & !a[2] & !b[2] & a[0];
A1L63_p4_out = b[0] & a[2] & !b[2] & !a[0] & a[3] & b[3];
A1L63_or_out = A1L76 # A1L63_p0_out # A1L63_p1_out # A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;
A1L63 = A1L63_or_out;


--A1L73 is reduce_or~1186
A1L73 = EXP(b[0] & a[1] & !b[1] & a[2] & b[2] & !a[0]);


--A1L83 is reduce_or~1187
A1L83 = EXP(b[0] & a[1] & !b[1] & !a[2] & !b[2] & !a[0]);


--A1L93 is reduce_or~1188
A1L93 = EXP(b[0] & !a[1] & b[1] & a[2] & !b[2] & !a[0]);


--A1L04 is reduce_or~1189
A1L04 = EXP(b[0] & !a[1] & b[1] & !a[2] & b[2] & !a[0]);


--A1L14 is reduce_or~1190
A1L14_p1_out = A1L73 & A1L83 & A1L93 & A1L04 & !A1L53 & !A1L63;
A1L14_or_out = A1L14_p1_out;
A1L14 = !(A1L14_or_out);


--A1L24 is reduce_or~1198
A1L24_p0_out = b[0] & a[1] & b[1] & a[3] & b[3] & !a[0];
A1L24_p1_out = !b[0] & a[1] & !b[1] & !a[2] & !a[3] & !b[3];
A1L24_p2_out = !b[0] & !a[1] & !b[1] & !a[2] & !a[3] & b[3];
A1L24_p3_out = b[0] & a[1] & b[1] & !a[3] & !b[3] & !a[0];
A1L24_p4_out = b[0] & !a[1] & !b[1] & a[3] & b[3] & !a[0];
A1L24_or_out = A1L86 # A1L24_p0_out # A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;
A1L24 = A1L24_or_out;


--A1L34 is reduce_or~1204
A1L34_p0_out = !b[0] & a[1] & !b[1] & !a[2] & !b[2];
A1L34_p1_out = !b[0] & a[1] & !b[1] & !a[2] & a[3] & b[3];
A1L34_p2_out = !b[0] & a[1] & b[1] & !a[3] & b[3] & b[2];
A1L34_p3_out = !b[0] & a[1] & b[1] & a[3] & !b[3] & b[2];
A1L34_p4_out = !b[0] & a[1] & !b[1] & a[2] & b[2];
A1L34_or_out = A1L96 # A1L34_p0_out # A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;
A1L34 = A1L34_or_out;


--A1L44 is reduce_or~1210
A1L44_p0_out = b[0] & a[0] & a[2] & a[3] & b[3] & !b[2];
A1L44_p1_out = b[0] & a[0] & !a[2] & a[3] & !b[3];
A1L44_p2_out = !b[0] & !a[0] & a[2] & !a[3] & !b[3] & !b[2];
A1L44_p3_out = !b[0] & !a[0] & a[2] & a[3] & b[3] & !b[2];
A1L44_p4_out = b[0] & a[0] & a[2] & !a[3] & !b[3] & !b[2];
A1L44_or_out = A1L07 # A1L44_p0_out # A1L44_p1_out # A1L44_p2_out # A1L44_p3_out # A1L44_p4_out;
A1L44 = A1L44_or_out;


--A1L54 is reduce_or~1216
A1L54_p0_out = !b[0] & a[0] & !b[2] & !a[3] & b[3] & a[1];
A1L54_p1_out = b[0] & a[0] & b[2] & a[3] & !b[3];
A1L54_p2_out = !a[0] & !b[2] & a[3] & !b[3] & !a[1] & b[1];
A1L54_p3_out = !a[0] & !b[2] & !a[3] & b[3] & !a[1] & b[1];
A1L54_p4_out = !b[0] & a[0] & !b[2] & a[3] & !b[3] & a[1];
A1L54_or_out = A1L17 # A1L54_p0_out # A1L54_p1_out # A1L54_p2_out # A1L54_p3_out # A1L54_p4_out;
A1L54 = A1L54_or_out;


--A1L64 is reduce_or~1222
A1L64_p0_out = b[0] & !a[0] & !a[2] & b[2] & !b[1];
A1L64_p1_out = !b[0] & a[0] & !a[1] & !a[2] & b[2];
A1L64_p2_out = b[0] & !a[0] & a[1] & a[2] & !b[2];
A1L64_p3_out = b[0] & !a[0] & a[1] & !a[2] & b[2];
A1L64_p4_out = b[0] & !a[0] & a[2] & !b[2] & !b[1];
A1L64_or_out = A1L27 # A1L64_p0_out # A1L64_p1_out # A1L64_p2_out # A1L64_p3_out # A1L64_p4_out;
A1L64 = A1L64_or_out;


--A1L74 is reduce_or~1223
A1L74_p1_out = !A1L24 & !A1L34 & !A1L44 & !A1L54 & !A1L64;
A1L74_or_out = A1L74_p1_out;
A1L74 = A1L74_or_out;


--A1L84 is reduce_or~1230
A1L84_p0_out = !a[0] & b[1] & a[1] & a[2] & !b[2] & !a[3] & !b[3] & !b[0];
A1L84_p1_out = a[0] & !b[1] & !a[1] & a[2] & !b[2] & !a[3] & !b[3] & b[0];
A1L84_p2_out = a[0] & !b[1] & !a[1] & !a[2] & b[2] & a[3] & !b[3] & b[0];
A1L84_p3_out = a[0] & !b[1] & !a[1] & !a[2] & b[2] & !a[3] & b[3] & b[0];
A1L84_p4_out = !a[0] & b[1] & a[1] & a[2] & !b[2] & a[3] & b[3] & !b[0];
A1L84_or_out = A1L37 # A1L84_p0_out # A1L84_p1_out # A1L84_p2_out # A1L84_p3_out # A1L84_p4_out;
A1L84 = A1L84_or_out;


--A1L94 is reduce_or~1236
A1L94_p0_out = b[1] & !a[1] & a[2] & !b[2] & !a[3] & b[3] & b[0];
A1L94_p1_out = !a[0] & !b[1] & !a[1] & !a[2] & b[2] & !a[3] & b[3] & !b[0];
A1L94_p2_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & a[3] & !b[3];
A1L94_p3_out = b[1] & !a[1] & a[2] & !b[2] & a[3] & !b[3] & b[0];
A1L94_p4_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & !a[3] & b[3];
A1L94_or_out = A1L47 # A1L94_p0_out # A1L94_p1_out # A1L94_p2_out # A1L94_p3_out # A1L94_p4_out;
A1L94 = A1L94_or_out;


--A1L05 is reduce_or~1242
A1L05_p0_out = !b[1] & a[1] & !a[2] & !b[2] & !a[3] & b[3] & !a[0];
A1L05_p1_out = !b[1] & a[1] & a[2] & b[2] & a[3] & !b[3] & b[0];
A1L05_p2_out = !b[1] & a[1] & a[2] & b[2] & !a[3] & b[3] & !a[0];
A1L05_p3_out = !b[1] & a[1] & a[2] & b[2] & !a[3] & b[3] & b[0];
A1L05_p4_out = !b[1] & a[1] & !a[2] & !b[2] & a[3] & !b[3] & !a[0];
A1L05_or_out = A1L57 # A1L05_p0_out # A1L05_p1_out # A1L05_p2_out # A1L05_p3_out # A1L05_p4_out;
A1L05 = A1L05_or_out;


--A1L15 is reduce_or~1248
A1L15_p0_out = !b[1] & a[1] & !a[2] & !b[2] & b[0] & !a[3] & b[3];
A1L15_p1_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & b[0];
A1L15_p2_out = a[0] & !b[1] & a[1] & a[2] & !b[2] & !b[0];
A1L15_p3_out = a[0] & !b[1] & a[1] & !a[2] & b[2] & !b[0];
A1L15_p4_out = !b[1] & a[1] & !a[2] & !b[2] & b[0] & a[3] & !b[3];
A1L15_or_out = A1L67 # A1L15_p0_out # A1L15_p1_out # A1L15_p2_out # A1L15_p3_out # A1L15_p4_out;
A1L15 = A1L15_or_out;


--A1L35 is reduce_or~1253
A1L35_p1_out = A1L25 & !A1L84 & !A1L94 & !A1L05 & !A1L15;
A1L35_or_out = A1L35_p1_out;
A1L35 = !(A1L35_or_out);


--A1L45 is reduce_or~1260
A1L45_p1_out = E3L3 & E3L1 & !E3L2;
A1L45_p2_out = E3L3 & E3L1 & E3L8;
A1L45_p3_out = E3L3 & !E3L1 & E3L2 & !E3L8;
A1L45_p4_out = !E3L1 & !E3L2 & E3L8;
A1L45_or_out = A1L45_p1_out # A1L45_p2_out # A1L45_p3_out # A1L45_p4_out;
A1L45 = A1L45_or_out;


--A1L65 is reduce_or~1272
A1L65_p0_out = !b[2] & a[2] & !a[0] & b[0];
A1L65_p1_out = b[2] & b[1] & !a[2] & a[0] & !b[0];
A1L65_p2_out = !b[2] & !b[1] & !a[2] & a[0] & !b[0];
A1L65_p3_out = !b[2] & b[1] & a[2] & a[0] & !b[0];
A1L65_p4_out = b[2] & !b[1] & a[2] & a[0] & !b[0];
A1L65_or_out = A1L65_p0_out # A1L65_p1_out # A1L65_p2_out # A1L65_p3_out # A1L65_p4_out;
A1L65 = A1L65_or_out;


--A1L75 is reduce_or~1278
A1L75_p0_out = !b[2] & b[1] & a[1] & !a[2] & a[0];
A1L75_p1_out = !b[2] & !b[1] & !a[1] & !a[2] & a[0];
A1L75_p2_out = !b[2] & !b[1] & !a[1] & !a[2] & !b[0];
A1L75_p3_out = b[2] & b[1] & a[1] & a[2] & a[0];
A1L75_p4_out = b[2] & !b[1] & !a[1] & a[2] & a[0];
A1L75_or_out = A1L75_p0_out # A1L75_p1_out # A1L75_p2_out # A1L75_p3_out # A1L75_p4_out;
A1L75 = A1L75_or_out;


--A1L85 is reduce_or~1284
A1L85_p0_out = b[1] & a[1] & !b[0] & b[2] & a[2];
A1L85_p1_out = !b[1] & !a[1] & a[0] & !b[0];
A1L85_p2_out = b[1] & a[1] & a[0] & !b[0];
A1L85_p3_out = b[1] & a[1] & !b[0] & !b[2] & !a[2];
A1L85_p4_out = !b[1] & !a[1] & !b[0] & b[2] & a[2];
A1L85_or_out = A1L85_p0_out # A1L85_p1_out # A1L85_p2_out # A1L85_p3_out # A1L85_p4_out;
A1L85 = A1L85_or_out;


--A1L95 is reduce_or~1290
A1L95_p0_out = b[2] & a[1] & b[3] & !a[3];
A1L95_p1_out = b[2] & a[1] & !b[3] & a[3];
A1L95_p2_out = !b[2] & a[1] & b[3] & a[3] & a[2];
A1L95_p3_out = b[2] & !b[3] & a[3] & a[2];
A1L95_p4_out = !b[2] & !b[3] & a[3] & !a[2];
A1L95_or_out = A1L95_p0_out # A1L95_p1_out # A1L95_p2_out # A1L95_p3_out # A1L95_p4_out;
A1L95 = A1L95_or_out;


--A1L06 is reduce_or~1296
A1L06_p0_out = b[2] & b[3] & !a[3] & a[2];