sub.fit.eqn

一些Verilog学习程序B

A1L46_p3_out = b[2] & !b[1] & b[3] & !a[3];
A1L46_p4_out = !b[2] & b[1] & b[3] & !a[3] & !a[1];
A1L46_or_out = A1L46_p0_out # A1L46_p1_out # A1L46_p2_out # A1L46_p3_out # A1L46_p4_out;
A1L46 = A1L46_or_out;


--A1L76 is reduce_or~1303 at LC97
A1L76_p1_out = A1L56 & A1L66 & !A1L06 & !A1L16 & !A1L26 & !A1L36 & !A1L46 & A1L95;
A1L76_or_out = A1L76_p1_out;
A1L76 = A1L76_or_out;


--E3L4 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~46 at LC23
E3L4_p0_out = !b[0] & a[1] & !b[2] & a[2] & b[1];
E3L4_p1_out = !b[0] & !a[1] & !b[2] & !a[2];
E3L4_p2_out = !a[1] & !b[2] & !a[2] & a[0];
E3L4_p3_out = !b[0] & !a[1] & b[2] & a[2];
E3L4_p4_out = !a[1] & b[2] & a[2] & a[0];
E3L4 = E3L4_p0_out # E3L4_p1_out # E3L4_p2_out # E3L4_p3_out # E3L4_p4_out;


--E3L5 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~52 at LC24
E3L5_p0_out = b[0] & !b[2] & !a[2] & b[1] & !a[0];
E3L5_p1_out = !b[0] & a[1] & b[2] & !a[2] & b[1];
E3L5_p2_out = a[1] & !b[2] & a[2] & b[1] & a[0];
E3L5_p3_out = a[1] & b[2] & !a[2] & b[1] & a[0];
E3L5_p4_out = b[0] & b[2] & a[2] & b[1] & !a[0];
E3L5 = E3L4 # E3L5_p0_out # E3L5_p1_out # E3L5_p2_out # E3L5_p3_out # E3L5_p4_out;


--E3L9 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~58 at LC100
E3L9_p1_out = !a[2] & b[1] & b[0] & !a[0];
E3L9_p2_out = !a[2] & b[1] & !a[1];
E3L9_p3_out = !a[2] & b[2];
E3L9 = E3L9_p1_out # E3L9_p2_out # E3L9_p3_out;


--A1L86 is reduce_or~1305 at LC81
A1L86_p0_out = !a[3] & b[3] & !a[1] & !a[2] & !b[0] & a[0];
A1L86_p1_out = !a[3] & !b[3] & !a[1] & !b[1] & a[2] & !b[2];
A1L86_p2_out = !a[3] & b[3] & !a[1] & !b[1] & !a[2] & b[2];
A1L86_p3_out = a[3] & !b[3] & !a[1] & !b[1] & !a[2] & b[2];
A1L86_p4_out = a[3] & !b[3] & !a[1] & !a[2] & !b[0] & a[0];
A1L86 = A1L86_p0_out # A1L86_p1_out # A1L86_p2_out # A1L86_p3_out # A1L86_p4_out;


--A1L96 is reduce_or~1311 at LC82
A1L96_p0_out = !a[3] & b[3] & a[1] & b[1] & !a[2] & b[2];
A1L96_p1_out = a[3] & b[3] & !a[1] & !b[1] & a[2] & !b[2];
A1L96_p2_out = !a[3] & !b[3] & a[1] & b[1] & a[2] & !b[2];
A1L96_p3_out = !a[3] & b[3] & !a[1] & b[2] & !b[0] & a[0];
A1L96_p4_out = a[3] & !b[3] & !a[1] & b[2] & !b[0] & a[0];
A1L96 = A1L86 # A1L96_p0_out # A1L96_p1_out # A1L96_p2_out # A1L96_p3_out # A1L96_p4_out;


--A1L07 is reduce_or~1317 at LC104
A1L07_p0_out = !a[3] & !b[3] & !b[0] & a[2] & a[0] & !b[1];
A1L07_p1_out = !a[3] & b[3] & b[0] & !a[2] & !a[0];
A1L07_p2_out = a[3] & !b[3] & b[0] & !a[2] & !a[0];
A1L07_p3_out = a[3] & !b[3] & b[0] & !a[0] & b[2];
A1L07_p4_out = !a[3] & b[3] & b[0] & !a[0] & b[2];
A1L07 = A1L07_p0_out # A1L07_p1_out # A1L07_p2_out # A1L07_p3_out # A1L07_p4_out;


--A1L17 is reduce_or~1323 at LC105
A1L17_p0_out = !b[0] & b[1] & b[2] & a[0] & a[2] & a[1];
A1L17_p1_out = a[3] & b[3] & !b[0] & !b[1] & !b[2] & a[0];
A1L17_p2_out = !a[3] & !b[3] & !b[0] & !b[1] & !b[2] & a[0];
A1L17_p3_out = a[3] & b[3] & !b[0] & !b[2] & a[0] & a[2];
A1L17_p4_out = !a[3] & !b[3] & !b[0] & !b[2] & a[0] & a[2];
A1L17 = A1L07 # A1L17_p0_out # A1L17_p1_out # A1L17_p2_out # A1L17_p3_out # A1L17_p4_out;


--A1L27 is reduce_or~1329 at LC7
A1L27_p0_out = b[0] & !a[1] & !b[1] & !a[3] & !b[3] & !a[0];
A1L27_p1_out = !b[0] & !a[1] & b[1] & !a[3] & !b[3];
A1L27_p2_out = a[1] & !b[1] & a[3] & !b[3] & !a[0];
A1L27_p3_out = a[1] & !b[1] & !a[3] & b[3] & !a[0];
A1L27_p4_out = !b[0] & !a[1] & b[1] & a[3] & b[3];
A1L27 = A1L27_p0_out # A1L27_p1_out # A1L27_p2_out # A1L27_p3_out # A1L27_p4_out;


--A1L37 is reduce_or~1335 at LC9
A1L37_p0_out = !a[1] & !b[1] & a[3] & !b[3] & !b[0] & b[2];
A1L37_p1_out = !a[1] & b[1] & !a[2] & !a[3] & !b[3];
A1L37_p2_out = !a[1] & b[1] & !a[2] & a[3] & b[3];
A1L37_p3_out = !a[1] & !b[1] & !a[2] & a[3] & !b[3] & !b[0];
A1L37_p4_out = !a[1] & !b[1] & !a[3] & b[3] & !b[0] & b[2];
A1L37 = A1L37_p0_out # A1L37_p1_out # A1L37_p2_out # A1L37_p3_out # A1L37_p4_out;


--A1L47 is reduce_or~1341 at LC21
A1L47_p0_out = b[0] & a[0] & !a[2] & !a[3] & b[3];
A1L47_p1_out = !b[0] & !a[0] & !a[2] & !a[3] & b[3];
A1L47_p2_out = !b[0] & !a[0] & !a[2] & a[3] & !b[3];
A1L47_p3_out = !b[0] & !a[0] & !a[3] & b[3] & b[2];
A1L47_p4_out = !b[0] & !a[0] & a[3] & !b[3] & b[2];
A1L47 = A1L47_p0_out # A1L47_p1_out # A1L47_p2_out # A1L47_p3_out # A1L47_p4_out;


--A1L57 is reduce_or~1347 at LC19
A1L57_p0_out = b[0] & a[0] & b[2] & !a[3] & b[3];
A1L57_p1_out = b[0] & a[0] & a[1] & !b[1];
A1L57_p2_out = b[0] & a[0] & !a[1] & b[1];
A1L57_p3_out = !b[0] & !a[0] & a[1] & !b[1];
A1L57_p4_out = !b[0] & !a[0] & !a[1] & b[1];
A1L57 = A1L57_p0_out # A1L57_p1_out # A1L57_p2_out # A1L57_p3_out # A1L57_p4_out;


--A1L67 is reduce_or~1353 at LC17
A1L67_p0_out = a[0] & !a[1] & a[2] & !b[2] & !b[0];
A1L67_p1_out = !a[0] & !a[1] & b[1] & !a[2] & !b[2];
A1L67_p2_out = !a[0] & !a[1] & b[1] & a[2] & b[2];
A1L67_p3_out = a[0] & b[1] & a[2] & !b[2] & !b[0];
A1L67_p4_out = a[0] & b[1] & !a[2] & b[2] & !b[0];
A1L67 = A1L67_p0_out # A1L67_p1_out # A1L67_p2_out # A1L67_p3_out # A1L67_p4_out;


--A1L77 is reduce_or~1359 at LC102
A1L77_p0_out = a[0] & !b[1] & !a[1] & a[2] & !b[2] & a[3] & b[3] & b[0];
A1L77_p1_out = a[0] & b[1] & a[1] & a[2] & !b[2] & a[3] & b[3] & b[0];
A1L77_p2_out = a[0] & b[1] & a[1] & a[2] & !b[2] & !a[3] & !b[3] & b[0];
A1L77_p3_out = a[0] & b[1] & a[1] & !a[2] & b[2] & a[3] & !b[3] & b[0];
A1L77_p4_out = a[0] & b[1] & a[1] & !a[2] & b[2] & !a[3] & b[3] & b[0];
A1L77 = A1L77_p0_out # A1L77_p1_out # A1L77_p2_out # A1L77_p3_out # A1L77_p4_out;


--A1L87 is reduce_or~1365 at LC1
A1L87_p0_out = !a[0] & !b[1] & !a[1] & !a[2] & b[2] & a[3] & !b[3] & !b[0];
A1L87_p1_out = !a[0] & b[1] & a[1] & !a[2] & b[2] & a[3] & !b[3] & !b[0];
A1L87_p2_out = !a[0] & b[1] & a[1] & !a[2] & b[2] & !a[3] & b[3] & !b[0];
A1L87_p3_out = !a[0] & !b[1] & !a[1] & a[2] & !b[2] & a[3] & b[3] & !b[0];
A1L87_p4_out = !a[0] & !b[1] & !a[1] & a[2] & !b[2] & !a[3] & !b[3] & !b[0];
A1L87 = A1L87_p0_out # A1L87_p1_out # A1L87_p2_out # A1L87_p3_out # A1L87_p4_out;


--A1L97 is reduce_or~1371 at LC5
A1L97_p0_out = !a[0] & !b[1] & a[1] & a[2] & b[2] & a[3] & !b[3];
A1L97_p1_out = !a[0] & b[1] & !a[1] & !a[2] & b[2] & a[3] & b[3];
A1L97_p2_out = b[1] & !a[1] & !a[2] & b[2] & a[3] & b[3] & b[0];
A1L97_p3_out = !a[0] & b[1] & !a[1] & !a[2] & b[2] & !a[3] & !b[3];
A1L97_p4_out = b[1] & !a[1] & !a[2] & b[2] & !a[3] & !b[3] & b[0];
A1L97 = A1L97_p0_out # A1L97_p1_out # A1L97_p2_out # A1L97_p3_out # A1L97_p4_out;


--A1L08 is reduce_or~1377 at LC3
A1L08_p0_out = !a[0] & b[1] & !a[2] & b[2] & b[0] & !a[1];
A1L08_p1_out = !a[0] & !b[1] & !a[2] & !b[2] & b[0];
A1L08_p2_out = !a[0] & !a[2] & !b[2] & b[0] & a[1];
A1L08_p3_out = !a[0] & !b[1] & a[2] & b[2] & b[0];
A1L08_p4_out = !a[0] & a[2] & b[2] & b[0] & a[1];
A1L08 = A1L08_p0_out # A1L08_p1_out # A1L08_p2_out # A1L08_p3_out # A1L08_p4_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC118
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--A1L62 is reduce_or~1120sexp3 at SEXP96
A1L62 = EXP(b[0] & !b[1] & a[2] & !b[2] & !a[0] & !a[3] & b[3] & a[1]);


--A1L72 is reduce_or~1120sexp4 at SEXP94
A1L72 = EXP(!b[0] & !b[1] & !a[2] & b[2] & a[0] & a[3] & !b[3] & a[1]);


--A1L82 is reduce_or~1120sexp5 at SEXP93
A1L82 = EXP(!b[0] & !b[1] & !a[2] & b[2] & a[0] & !a[3] & b[3] & a[1]);


--A1L95 is reduce_or~1266sexp5 at SEXP97
A1L95 = EXP(!b[2] & !b[1] & a[2] & b[3] & a[3]);


--A1L63 is reduce_or~1163bal at LC90
A1L63_p0_out = b[1] & a[2] & !b[2] & !a[3] & b[3] & a[1] & !b[0] & a[0];
A1L63_p1_out = b[1] & !a[2] & b[2] & a[3] & !b[3] & !a[1];
A1L63_p2_out = b[1] & a[2] & !b[2] & a[3] & b[3] & !a[1];
A1L63_p3_out = !b[1] & a[2] & b[2] & a[3] & b[3] & a[1];
A1L63_p4_out = b[1] & a[2] & !b[2] & a[3] & !b[3] & a[1] & !b[0] & a[0];
A1L63_or_out = A1L63_p0_out # A1L63_p1_out # A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;
A1L63 = !(A1L63_or_out);


--A1L66 is reduce_or~1302bal at LC92
A1L66_p0_out = !b[3] & !a[3] & !b[2] & a[1] & a[2];
A1L66_p1_out = !b[3] & a[3] & !a[0] & b[0];
A1L66_p2_out = !b[3] & !a[3] & b[2] & b[1] & !a[1] & !a[2];
A1L66_p3_out = b[3] & a[3] & b[2] & b[1] & !a[1] & !a[2];
A1L66_p4_out = !b[3] & !a[3] & !b[2] & !b[1] & a[2];
A1L66_or_out = A1L66_p0_out # A1L66_p1_out # A1L66_p2_out # A1L66_p3_out # A1L66_p4_out;
A1L66 = !(A1L66_or_out);


--A1L56 is reduce_or~1297bal at LC95
A1L56_p0_out = b[3] & !a[3] & !a[0] & b[0];
A1L56_p1_out = !b[2] & !a[2] & b[3] & !a[3];
A1L56_p2_out = b[1] & !a[1] & !a[0] & b[0];
A1L56_p3_out = !b[1] & a[1] & !a[0] & b[0];
A1L56_p4_out = b[2] & !a[2] & !a[0] & b[0];
A1L56_or_out = A1L56_p0_out # A1L56_p1_out # A1L56_p2_out # A1L56_p3_out # A1L56_p4_out;
A1L56 = !(A1L56_or_out);


--A1L52 is reduce_or~1114sexp3bal at LC112
A1L52_p0_out = !b[0] & a[2] & b[2] & a[0] & !a[3] & !b[3] & a[1];
A1L52_p1_out = !b[0] & !b[1] & a[2] & !b[2] & a[0] & a[3] & !b[3] & !a[1];
A1L52_p2_out = !b[0] & !b[1] & a[2] & !b[2] & a[0] & !a[3] & b[3] & !a[1];
A1L52_p3_out = b[0] & !b[1] & a[2] & !b[2] & !a[0] & a[3] & !b[3] & a[1];
A1L52_p4_out = !b[0] & !b[1] & a[2] & b[2] & a[0] & !a[3] & !b[3];
A1L52_or_out = A1L52_p0_out # A1L52_p1_out # A1L52_p2_out # A1L52_p3_out # A1L52_p4_out;
A1L52 = !(A1L52_or_out);


--A1L65 is reduce_or~1249bal at LC96
A1L65_p1_out = a[0] & b[1] & a[2] & b[2] & !b[0];
A1L65_p2_out = a[0] & b[1] & !a[2] & !b[2] & !b[0];
A1L65_p3_out = a[0] & a[2] & b[2] & !b[0] & !a[1];
A1L65_p4_out = a[0] & !a[2] & !b[2] & !b[0] & !a[1];
A1L65_or_out = A1L65_p1_out # A1L65_p2_out # A1L65_p3_out # A1L65_p4_out;
A1L65 = !(A1L65_or_out);


--a[0] is a[0] at PIN_24
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_22
--operation mode is input

a[1] = INPUT();


--a[2] is a[2] at PIN_21
--operation mode is input

a[2] = INPUT();


--a[3] is a[3] at PIN_20
--operation mode is input

a[3] = INPUT();


--b[0] is b[0] at PIN_18
--operation mode is input

b[0] = INPUT();


--b[1] is b[1] at PIN_17
--operation mode is input

b[1] = INPUT();


--b[2] is b[2] at PIN_16
--operation mode is input

b[2] = INPUT();


--b[3] is b[3] at PIN_15
--operation mode is input

b[3] = INPUT();


--c[0] is c[0] at PIN_61
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en is en at PIN_75
--operation mode is output

en = OUTPUT(~GND~0);


--c[2] is c[2] at PIN_56
--operation mode is output

c[2] = OUTPUT(A1L73);


--c[3] is c[3] at PIN_58
--operation mode is output

c[3] = OUTPUT(A1L54);


--c[7] is c[7] at PIN_57
--operation mode is output

c[7] = OUTPUT(A1L83);


--c[1] is c[1] at PIN_64
--operation mode is output

c[1] = OUTPUT(A1L15);


--c[4] is c[4] at PIN_60
--operation mode is output

c[4] = OUTPUT(A1L75);


--c[6] is c[6] at PIN_55
--operation mode is output

c[6] = OUTPUT(A1L85);


--c[5] is c[5] at PIN_63
--operation mode is output

c[5] = OUTPUT(A1L76);