sub.fit.eqn

一些Verilog学习程序B

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--E3L1 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[1]~24 at LC11
E3L1_p1_out = b[0] & a[0];
E3L1_p2_out = !b[0] & !a[0];
E3L1_or_out = E3L1_p1_out # E3L1_p2_out;
E3L1 = E3L1_or_out;


--E3L2 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[2]~25 at LC12
E3L2_p1_out = b[0] & !a[0];
E3L2_p2_out = b[1] & a[1];
E3L2_p3_out = !b[1] & !a[1];
E3L2_or_out = E3L2_p2_out # E3L2_p3_out;
E3L2 = E3L2_p1_out $ E3L2_or_out;


--E3L3 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[3]~30 at LC25
E3L3_p0_out = a[1] & b[2] & a[2] & !b[1];
E3L3_p2_out = b[0] & !a[1] & b[2] & !a[2] & !b[1] & !a[0];
E3L3_p3_out = b[0] & !a[1] & !b[2] & a[2] & !b[1] & !a[0];
E3L3_p4_out = a[1] & !b[2] & !a[2] & !b[1];
E3L3_or_out = E3L5 # E3L3_p0_out # E3L3_p2_out # E3L3_p3_out # E3L3_p4_out;
E3L3 = !b[1] $ E3L3_or_out;


--E3L6 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~37 at SEXP100
E3L6 = EXP(b[3] & a[3]);


--E3L7 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~38 at SEXP99
E3L7 = EXP(!a[3] & !b[3]);


--E3L8 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|sout_node[4]~39 at LC101
E3L8_p1_out = E3L6 & E3L7;
E3L8_p0_out = b[0] & !a[1] & !a[0] & b[2];
E3L8_p2_out = !a[2] & b[0] & !a[1] & !a[0];
E3L8_p3_out = b[0] & !a[0] & b[1] & b[2];
E3L8_p4_out = !a[1] & b[1] & b[2];
E3L8_or_out = E3L9 # E3L8_p0_out # E3L8_p2_out # E3L8_p3_out # E3L8_p4_out;
E3L8 = E3L8_p1_out $ E3L8_or_out;


--A1L92 is reduce_or~1126 at LC84
A1L92_p0_out = b[0] & b[1] & a[2] & !b[2] & !a[0] & !a[3] & !b[3];
A1L92_p1_out = !b[0] & !b[1] & a[2] & b[2] & a[0] & a[3] & b[3];
A1L92_p2_out = !b[0] & b[1] & !a[2] & a[0] & a[3] & b[3] & a[1];
A1L92_p3_out = !b[0] & b[1] & !a[2] & a[0] & !a[3] & !b[3] & a[1];
A1L92_p4_out = b[0] & b[1] & a[2] & !b[2] & !a[0] & a[3] & b[3];
A1L92_or_out = A1L92_p0_out # A1L92_p1_out # A1L92_p2_out # A1L92_p3_out # A1L92_p4_out;
A1L92 = A1L92_or_out;


--A1L03 is reduce_or~1132 at LC107
A1L03_p0_out = b[0] & b[1] & a[2] & !a[0] & a[3] & b[3] & !a[1];
A1L03_p1_out = !b[0] & !b[1] & !a[2] & a[0] & a[3] & b[3] & !a[1];
A1L03_p2_out = !b[0] & !b[1] & !a[2] & a[0] & !a[3] & !b[3] & !a[1];
A1L03_p3_out = b[0] & !b[1] & !a[2] & !a[0] & a[3] & b[3] & a[1];
A1L03_p4_out = b[0] & !b[1] & !a[2] & !a[0] & !a[3] & !b[3] & a[1];
A1L03_or_out = A1L03_p0_out # A1L03_p1_out # A1L03_p2_out # A1L03_p3_out # A1L03_p4_out;
A1L03 = A1L03_or_out;


--A1L13 is reduce_or~1138 at LC87
A1L13_p0_out = b[0] & a[2] & !b[2] & !a[0] & !a[3] & !b[3] & !a[1];
A1L13_p1_out = !b[0] & a[2] & b[2] & a[0] & a[3] & b[3] & a[1];
A1L13_p2_out = b[0] & a[2] & !a[0] & !a[3] & !b[3] & !a[1] & b[1];
A1L13_p3_out = b[0] & !b[2] & !a[0] & a[3] & b[3] & !a[1] & b[1];
A1L13_p4_out = b[0] & a[2] & !b[2] & !a[0] & a[3] & b[3] & !a[1];
A1L13_or_out = A1L13_p0_out # A1L13_p1_out # A1L13_p2_out # A1L13_p3_out # A1L13_p4_out;
A1L13 = A1L13_or_out;


--A1L23 is reduce_or~1144 at LC108
A1L23_p0_out = !b[0] & b[1] & b[2] & a[0] & !a[3] & b[3] & !a[1];
A1L23_p1_out = b[0] & b[1] & !b[2] & !a[0] & !a[3] & !b[3] & !a[1];
A1L23_p2_out = !b[0] & !b[1] & !b[2] & a[0] & a[3] & b[3] & a[1];
A1L23_p3_out = !b[0] & !b[1] & !b[2] & a[0] & !a[3] & !b[3] & a[1];
A1L23_p4_out = !b[0] & b[1] & b[2] & a[0] & a[3] & !b[3] & !a[1];
A1L23_or_out = A1L23_p0_out # A1L23_p1_out # A1L23_p2_out # A1L23_p3_out # A1L23_p4_out;
A1L23 = A1L23_or_out;


--A1L33 is reduce_or~1150 at LC109
A1L33_p0_out = b[0] & !b[1] & !a[2] & !a[0] & a[3] & !b[3] & !a[1];
A1L33_p1_out = !b[0] & b[1] & !a[2] & a[0] & a[3] & !b[3] & !a[1];
A1L33_p2_out = !b[0] & b[1] & !a[2] & a[0] & !a[3] & b[3] & !a[1];
A1L33_p3_out = b[0] & b[1] & !a[2] & !a[0] & a[3] & !b[3] & a[1];
A1L33_p4_out = b[0] & b[1] & !a[2] & !a[0] & !a[3] & b[3] & a[1];
A1L33_or_out = A1L33_p0_out # A1L33_p1_out # A1L33_p2_out # A1L33_p3_out # A1L33_p4_out;
A1L33 = A1L33_or_out;


--A1L43 is reduce_or~1156 at LC89
A1L43_p0_out = b[0] & !b[1] & !a[0] & !a[3] & b[3] & !a[1] & !a[2];
A1L43_p1_out = b[0] & b[1] & b[2] & !a[0] & a[3] & !b[3] & a[1];
A1L43_p2_out = b[0] & b[1] & b[2] & !a[0] & !a[3] & b[3] & a[1];
A1L43_p3_out = b[0] & !b[1] & b[2] & !a[0] & a[3] & !b[3] & !a[1];
A1L43_p4_out = b[0] & !b[1] & b[2] & !a[0] & !a[3] & b[3] & !a[1];
A1L43_or_out = A1L43_p0_out # A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--A1L53 is reduce_or~1162 at LC110
A1L53_p0_out = b[1] & !a[2] & b[2] & !a[3] & b[3] & !a[1];
A1L53_p1_out = !b[1] & !a[2] & !b[2] & !a[3] & !b[3] & a[1];
A1L53_p2_out = b[1] & a[2] & !b[2] & !a[3] & !b[3] & !a[1];
A1L53_p3_out = !b[1] & !a[2] & !b[2] & a[3] & b[3] & a[1];
A1L53_p4_out = !b[1] & a[2] & b[2] & !a[3] & !b[3] & a[1];
A1L53_or_out = A1L53_p0_out # A1L53_p1_out # A1L53_p2_out # A1L53_p3_out # A1L53_p4_out;
A1L53 = A1L53_or_out;


--A1L73 is reduce_or~1166 at LC86
A1L73_p1_out = A1L63 & !A1L92 & !A1L03 & !A1L13 & !A1L23 & !A1L33 & !A1L43 & !A1L53 & A1L52 & A1L62 & A1L72 & A1L82;
A1L73_or_out = A1L73_p1_out;
A1L73 = !(A1L73_or_out);


--A1L83 is reduce_or~1173 at LC88
A1L83_p1_out = E3L1 & !E3L8 & E3L2 & E3L3;
A1L83_p2_out = !E3L1 & !E3L8 & E3L2 & !E3L3;
A1L83_p3_out = !E3L1 & E3L8 & E3L2 & E3L3;
A1L83_p4_out = !E3L1 & E3L8 & !E3L2 & !E3L3;
A1L83_or_out = A1L83_p1_out # A1L83_p2_out # A1L83_p3_out # A1L83_p4_out;
A1L83 = A1L83_or_out;


--A1L93 is reduce_or~1179 at LC83
A1L93_p0_out = a[3] & b[3] & !b[1] & a[2] & !b[0] & a[0];
A1L93_p1_out = a[3] & !b[3] & a[1] & b[1] & !a[2] & b[2];
A1L93_p2_out = a[3] & b[3] & a[1] & b[1] & a[2] & !b[2];
A1L93_p3_out = a[3] & !b[3] & !a[2] & b[2] & !b[0] & a[0];
A1L93_p4_out = !a[3] & b[3] & !a[2] & b[2] & !b[0] & a[0];
A1L93_or_out = A1L96 # A1L93_p0_out # A1L93_p1_out # A1L93_p2_out # A1L93_p3_out # A1L93_p4_out;
A1L93 = A1L93_or_out;


--A1L04 is reduce_or~1185 at LC106
A1L04_p0_out = b[0] & a[2] & !b[2] & !a[0] & !a[3] & !b[3];
A1L04_p1_out = !b[0] & a[1] & b[1] & !a[2] & !b[2] & a[0];
A1L04_p2_out = !b[0] & !a[1] & !b[1] & a[2] & b[2] & a[0];
A1L04_p3_out = !b[0] & !a[1] & !b[1] & !a[2] & !b[2] & a[0];
A1L04_p4_out = b[0] & a[2] & !b[2] & !a[0] & a[3] & b[3];
A1L04_or_out = A1L17 # A1L04_p0_out # A1L04_p1_out # A1L04_p2_out # A1L04_p3_out # A1L04_p4_out;
A1L04 = A1L04_or_out;


--A1L14 is reduce_or~1186 at SEXP86
A1L14 = EXP(b[0] & a[1] & !b[1] & a[2] & b[2] & !a[0]);


--A1L24 is reduce_or~1187 at SEXP85
A1L24 = EXP(b[0] & a[1] & !b[1] & !a[2] & !b[2] & !a[0]);


--A1L34 is reduce_or~1188 at SEXP88
A1L34 = EXP(b[0] & !a[1] & b[1] & a[2] & !b[2] & !a[0]);


--A1L44 is reduce_or~1189 at SEXP91
A1L44 = EXP(b[0] & !a[1] & b[1] & !a[2] & b[2] & !a[0]);


--A1L54 is reduce_or~1190 at LC91
A1L54_p1_out = A1L14 & A1L24 & A1L34 & A1L44 & !A1L93 & !A1L04;
A1L54_or_out = A1L54_p1_out;
A1L54 = !(A1L54_or_out);


--A1L64 is reduce_or~1198 at LC8
A1L64_p0_out = b[0] & a[1] & b[1] & a[3] & b[3] & !a[0];
A1L64_p1_out = !b[0] & a[1] & !b[1] & !a[2] & !a[3] & !b[3];
A1L64_p2_out = !b[0] & !a[1] & !b[1] & !a[2] & !a[3] & b[3];
A1L64_p3_out = b[0] & a[1] & b[1] & !a[3] & !b[3] & !a[0];
A1L64_p4_out = b[0] & !a[1] & !b[1] & a[3] & b[3] & !a[0];
A1L64_or_out = A1L27 # A1L64_p0_out # A1L64_p1_out # A1L64_p2_out # A1L64_p3_out # A1L64_p4_out;
A1L64 = A1L64_or_out;


--A1L74 is reduce_or~1204 at LC10
A1L74_p0_out = !b[0] & a[1] & !b[1] & !a[2] & !b[2];
A1L74_p1_out = !b[0] & a[1] & !b[1] & !a[2] & a[3] & b[3];
A1L74_p2_out = !b[0] & a[1] & b[1] & !a[3] & b[3] & b[2];
A1L74_p3_out = !b[0] & a[1] & b[1] & a[3] & !b[3] & b[2];
A1L74_p4_out = !b[0] & a[1] & !b[1] & a[2] & b[2];
A1L74_or_out = A1L37 # A1L74_p0_out # A1L74_p1_out # A1L74_p2_out # A1L74_p3_out # A1L74_p4_out;
A1L74 = A1L74_or_out;


--A1L84 is reduce_or~1210 at LC22
A1L84_p0_out = b[0] & a[0] & a[2] & a[3] & b[3] & !b[2];
A1L84_p1_out = b[0] & a[0] & !a[2] & a[3] & !b[3];
A1L84_p2_out = !b[0] & !a[0] & a[2] & !a[3] & !b[3] & !b[2];
A1L84_p3_out = !b[0] & !a[0] & a[2] & a[3] & b[3] & !b[2];
A1L84_p4_out = b[0] & a[0] & a[2] & !a[3] & !b[3] & !b[2];
A1L84_or_out = A1L47 # A1L84_p0_out # A1L84_p1_out # A1L84_p2_out # A1L84_p3_out # A1L84_p4_out;
A1L84 = A1L84_or_out;


--A1L94 is reduce_or~1216 at LC20
A1L94_p0_out = !b[0] & a[0] & !b[2] & !a[3] & b[3] & a[1];
A1L94_p1_out = b[0] & a[0] & b[2] & a[3] & !b[3];
A1L94_p2_out = !a[0] & !b[2] & a[3] & !b[3] & !a[1] & b[1];
A1L94_p3_out = !a[0] & !b[2] & !a[3] & b[3] & !a[1] & b[1];
A1L94_p4_out = !b[0] & a[0] & !b[2] & a[3] & !b[3] & a[1];
A1L94_or_out = A1L57 # A1L94_p0_out # A1L94_p1_out # A1L94_p2_out # A1L94_p3_out # A1L94_p4_out;
A1L94 = A1L94_or_out;


--A1L05 is reduce_or~1222 at LC18
A1L05_p0_out = b[0] & !a[0] & !a[2] & b[2] & !b[1];
A1L05_p1_out = !b[0] & a[0] & !a[1] & !a[2] & b[2];
A1L05_p2_out = b[0] & !a[0] & a[1] & a[2] & !b[2];
A1L05_p3_out = b[0] & !a[0] & a[1] & !a[2] & b[2];
A1L05_p4_out = b[0] & !a[0] & a[2] & !b[2] & !b[1];
A1L05_or_out = A1L67 # A1L05_p0_out # A1L05_p1_out # A1L05_p2_out # A1L05_p3_out # A1L05_p4_out;
A1L05 = A1L05_or_out;


--A1L15 is reduce_or~1223 at LC99
A1L15_p1_out = !A1L64 & !A1L74 & !A1L84 & !A1L94 & !A1L05;
A1L15_or_out = A1L15_p1_out;
A1L15 = A1L15_or_out;


--A1L25 is reduce_or~1230 at LC103
A1L25_p0_out = !a[0] & b[1] & a[1] & a[2] & !b[2] & !a[3] & !b[3] & !b[0];
A1L25_p1_out = a[0] & !b[1] & !a[1] & a[2] & !b[2] & !a[3] & !b[3] & b[0];
A1L25_p2_out = a[0] & !b[1] & !a[1] & !a[2] & b[2] & a[3] & !b[3] & b[0];
A1L25_p3_out = a[0] & !b[1] & !a[1] & !a[2] & b[2] & !a[3] & b[3] & b[0];
A1L25_p4_out = !a[0] & b[1] & a[1] & a[2] & !b[2] & a[3] & b[3] & !b[0];
A1L25_or_out = A1L77 # A1L25_p0_out # A1L25_p1_out # A1L25_p2_out # A1L25_p3_out # A1L25_p4_out;
A1L25 = A1L25_or_out;


--A1L35 is reduce_or~1236 at LC2
A1L35_p0_out = b[1] & !a[1] & a[2] & !b[2] & !a[3] & b[3] & b[0];
A1L35_p1_out = !a[0] & !b[1] & !a[1] & !a[2] & b[2] & !a[3] & b[3] & !b[0];
A1L35_p2_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & a[3] & !b[3];
A1L35_p3_out = b[1] & !a[1] & a[2] & !b[2] & a[3] & !b[3] & b[0];
A1L35_p4_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & !a[3] & b[3];
A1L35_or_out = A1L87 # A1L35_p0_out # A1L35_p1_out # A1L35_p2_out # A1L35_p3_out # A1L35_p4_out;
A1L35 = A1L35_or_out;


--A1L45 is reduce_or~1242 at LC6
A1L45_p0_out = !b[1] & a[1] & !a[2] & !b[2] & !a[3] & b[3] & !a[0];
A1L45_p1_out = !b[1] & a[1] & a[2] & b[2] & a[3] & !b[3] & b[0];
A1L45_p2_out = !b[1] & a[1] & a[2] & b[2] & !a[3] & b[3] & !a[0];
A1L45_p3_out = !b[1] & a[1] & a[2] & b[2] & !a[3] & b[3] & b[0];
A1L45_p4_out = !b[1] & a[1] & !a[2] & !b[2] & a[3] & !b[3] & !a[0];
A1L45_or_out = A1L97 # A1L45_p0_out # A1L45_p1_out # A1L45_p2_out # A1L45_p3_out # A1L45_p4_out;
A1L45 = A1L45_or_out;


--A1L55 is reduce_or~1248 at LC4
A1L55_p0_out = !b[1] & a[1] & !a[2] & !b[2] & b[0] & !a[3] & b[3];
A1L55_p1_out = !a[0] & b[1] & !a[1] & a[2] & !b[2] & b[0];
A1L55_p2_out = a[0] & !b[1] & a[1] & a[2] & !b[2] & !b[0];
A1L55_p3_out = a[0] & !b[1] & a[1] & !a[2] & b[2] & !b[0];
A1L55_p4_out = !b[1] & a[1] & !a[2] & !b[2] & b[0] & a[3] & !b[3];
A1L55_or_out = A1L08 # A1L55_p0_out # A1L55_p1_out # A1L55_p2_out # A1L55_p3_out # A1L55_p4_out;
A1L55 = A1L55_or_out;


--A1L75 is reduce_or~1253 at LC93
A1L75_p1_out = A1L65 & !A1L25 & !A1L35 & !A1L45 & !A1L55;
A1L75_or_out = A1L75_p1_out;
A1L75 = !(A1L75_or_out);


--A1L85 is reduce_or~1260 at LC85
A1L85_p1_out = E3L3 & E3L1 & !E3L2;
A1L85_p2_out = E3L3 & E3L1 & E3L8;
A1L85_p3_out = E3L3 & !E3L1 & E3L2 & !E3L8;
A1L85_p4_out = !E3L1 & !E3L2 & E3L8;
A1L85_or_out = A1L85_p1_out # A1L85_p2_out # A1L85_p3_out # A1L85_p4_out;
A1L85 = A1L85_or_out;


--A1L06 is reduce_or~1272 at LC13
A1L06_p0_out = !b[2] & a[2] & !a[0] & b[0];
A1L06_p1_out = b[2] & b[1] & !a[2] & a[0] & !b[0];
A1L06_p2_out = !b[2] & !b[1] & !a[2] & a[0] & !b[0];
A1L06_p3_out = !b[2] & b[1] & a[2] & a[0] & !b[0];
A1L06_p4_out = b[2] & !b[1] & a[2] & a[0] & !b[0];
A1L06_or_out = A1L06_p0_out # A1L06_p1_out # A1L06_p2_out # A1L06_p3_out # A1L06_p4_out;
A1L06 = A1L06_or_out;


--A1L16 is reduce_or~1278 at LC111
A1L16_p0_out = !b[2] & b[1] & a[1] & !a[2] & a[0];
A1L16_p1_out = !b[2] & !b[1] & !a[1] & !a[2] & a[0];
A1L16_p2_out = !b[2] & !b[1] & !a[1] & !a[2] & !b[0];
A1L16_p3_out = b[2] & b[1] & a[1] & a[2] & a[0];
A1L16_p4_out = b[2] & !b[1] & !a[1] & a[2] & a[0];
A1L16_or_out = A1L16_p0_out # A1L16_p1_out # A1L16_p2_out # A1L16_p3_out # A1L16_p4_out;
A1L16 = A1L16_or_out;


--A1L26 is reduce_or~1284 at LC98
A1L26_p0_out = b[1] & a[1] & !b[0] & b[2] & a[2];
A1L26_p1_out = !b[1] & !a[1] & a[0] & !b[0];
A1L26_p2_out = b[1] & a[1] & a[0] & !b[0];
A1L26_p3_out = b[1] & a[1] & !b[0] & !b[2] & !a[2];
A1L26_p4_out = !b[1] & !a[1] & !b[0] & b[2] & a[2];
A1L26_or_out = A1L26_p0_out # A1L26_p1_out # A1L26_p2_out # A1L26_p3_out # A1L26_p4_out;
A1L26 = A1L26_or_out;


--A1L36 is reduce_or~1290 at LC15
A1L36_p0_out = b[2] & a[1] & b[3] & !a[3];
A1L36_p1_out = b[2] & a[1] & !b[3] & a[3];
A1L36_p2_out = !b[2] & a[1] & b[3] & a[3] & a[2];
A1L36_p3_out = b[2] & !b[3] & a[3] & a[2];
A1L36_p4_out = !b[2] & !b[3] & a[3] & !a[2];
A1L36_or_out = A1L36_p0_out # A1L36_p1_out # A1L36_p2_out # A1L36_p3_out # A1L36_p4_out;
A1L36 = A1L36_or_out;


--A1L46 is reduce_or~1296 at LC14
A1L46_p0_out = b[2] & b[3] & !a[3] & a[2];
A1L46_p1_out = b[2] & !b[1] & !b[3] & a[3];
A1L46_p2_out = !b[2] & b[1] & !b[3] & a[3] & !a[1];