add.map.eqn

一些Verilog学习程序B

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--A1L91 is reduce_or~2800
A1L91 = EXP(a[2] & b[2] & !a[0]);


--A1L02 is reduce_or~2801
A1L02 = EXP(!b[1] & !a[1]);


--A1L12 is reduce_or~2802
A1L12 = EXP(!b[2] & !a[2]);


--A1L22 is reduce_or~2803
A1L22 = EXP(b[2] & a[2]);


--A1L32 is reduce_or~2804
A1L32 = EXP(b[1] & a[1]);


--A1L42 is reduce_or~2810
A1L42_p0_out = a[2] & !b[0] & !a[0] & A1L32;
A1L42_p1_out = A1L91 & a[1] & b[1];
A1L42_p2_out = A1L02 & !a[2] & !b[2];
A1L42_p3_out = !a[1] & !b[1] & A1L12;
A1L42_p4_out = A1L22 & b[0] & a[0];
A1L42_or_out = A1L63 # A1L42_p0_out # A1L42_p1_out # A1L42_p2_out # A1L42_p3_out # A1L42_p4_out;
A1L42 = !(A1L42_or_out);


--A1L82 is reduce_or~2824
A1L82_p1_out = A1L62 & A1L72 & A1L52;
A1L82_or_out = A1L82_p1_out;
A1L82 = A1L82_or_out;


--A1L92 is reduce_or~2831
A1L92_p0_out = !b[0] & !a[0] & !a[1] & a[2] & b[2] & b[1];
A1L92_p1_out = !b[0] & a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L92_p2_out = b[0] & !a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L92_p3_out = b[0] & !a[0] & a[1] & !a[2] & b[2];
A1L92_p4_out = !b[0] & !a[0] & a[1] & a[2] & b[2] & !b[1];
A1L92_or_out = A1L73 # A1L92_p0_out # A1L92_p1_out # A1L92_p2_out # A1L92_p3_out # A1L92_p4_out;
A1L92 = A1L92_or_out;


--A1L03 is reduce_or~2837
A1L03_p0_out = b[0] & a[1] & !a[2] & b[2] & b[1];
A1L03_p1_out = !b[0] & a[0] & a[1] & a[2] & !b[2];
A1L03_p2_out = !b[0] & a[0] & a[2] & !b[2] & b[1];
A1L03_p3_out = b[0] & !a[1] & a[2] & b[2] & !b[1];
A1L03_p4_out = a[0] & !a[1] & a[2] & b[2] & !b[1];
A1L03_or_out = A1L83 # A1L03_p0_out # A1L03_p1_out # A1L03_p2_out # A1L03_p3_out # A1L03_p4_out;
A1L03 = A1L03_or_out;


--A1L13 is reduce_or~2839
A1L13_p1_out = b[0] & a[1] & a[2] & !b[2] & b[1];
A1L13_or_out = A1L13_p1_out # A1L92 # A1L03;
A1L13 = A1L13_or_out;


--A1L23 is reduce_or~2848
A1L23_p0_out = b[0] & a[0] & a[2] & b[2] & A1L02;
A1L23_p1_out = !b[0] & !a[0] & a[2] & b[2] & a[1] & b[1];
A1L23_p2_out = !b[0] & !a[0] & !a[2] & !b[2] & a[1] & !b[1];
A1L23_p3_out = !b[0] & !a[0] & !a[2] & !b[2] & !a[1] & b[1];
A1L23_p4_out = b[0] & a[0] & !a[2] & !b[2] & !a[1] & !b[1];
A1L23_or_out = A1L23_p0_out # A1L23_p1_out # A1L23_p2_out # A1L23_p3_out # A1L23_p4_out;
A1L23 = A1L23_or_out;


--A1L33 is reduce_or~2855
A1L33_p0_out = !b[0] & a[0] & a[2] & b[2] & A1L02;
A1L33_p1_out = !b[1] & b[0] & a[0] & a[1] & !a[2] & !b[2];
A1L33_p2_out = !b[1] & !b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L33_p3_out = !b[1] & b[0] & !a[0] & !a[1] & !a[2] & !b[2];
A1L33_p4_out = b[0] & !a[0] & a[2] & b[2] & A1L02;
A1L33_or_out = A1L93 # A1L33_p0_out # A1L33_p1_out # A1L33_p2_out # A1L33_p3_out # A1L33_p4_out;
A1L33 = A1L33_or_out;


--A1L43 is reduce_or~2861
A1L43_p0_out = !b[2] & !a[0] & b[0];
A1L43_p1_out = !a[2] & !b[2] & !a[0] & a[1] & b[1];
A1L43_p2_out = !a[2] & !b[2] & !a[1] & b[1] & b[0];
A1L43_p3_out = !a[2] & !b[2] & a[1] & !b[1] & b[0];
A1L43_p4_out = !b[2] & a[0] & !b[0];
A1L43_or_out = A1L14 # A1L43_p0_out # A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--A1L53 is reduce_or~2862
A1L53_p0_out = !a[2] & !a[1] & !b[2];
A1L53_p2_out = a[0] & b[1] & !a[2] & !a[1];
A1L53_p3_out = b[1] & !a[1] & b[0] & !b[2];
A1L53_p4_out = a[0] & b[1] & !a[1] & !b[2];
A1L53_or_out = A1L34 # A1L53_p0_out # A1L53_p2_out # A1L53_p3_out # A1L53_p4_out;
A1L53 = !a[1] $ A1L53_or_out;


--A1L63 is reduce_or~2869
A1L63_p1_out = !a[2] & !b[0] & !a[0] & b[2];
A1L63_p2_out = a[2] & b[0] & !a[0] & b[2];
A1L63_p3_out = a[2] & !b[0] & a[0] & b[2];
A1L63 = A1L63_p1_out # A1L63_p2_out # A1L63_p3_out;


--A1L73 is reduce_or~2873
A1L73_p0_out = b[0] & a[0] & a[1] & !a[2] & !b[2] & !b[1];
A1L73_p1_out = !b[0] & !a[0] & !a[1] & a[2] & !b[2] & !b[1];
A1L73_p2_out = !b[0] & !a[0] & !a[1] & !a[2] & b[2] & !b[1];
A1L73_p3_out = !b[0] & !a[0] & a[1] & !a[2] & !b[2] & b[1];
A1L73_p4_out = b[0] & a[0] & !a[1] & !a[2] & !b[2] & b[1];
A1L73 = A1L73_p0_out # A1L73_p1_out # A1L73_p2_out # A1L73_p3_out # A1L73_p4_out;


--A1L83 is reduce_or~2879
A1L83_p0_out = !b[0] & a[0] & !a[2] & b[2] & b[1];
A1L83_p1_out = b[0] & !a[0] & !a[2] & b[2] & b[1];
A1L83_p2_out = b[0] & !a[0] & a[2] & !b[2] & a[1];
A1L83_p3_out = b[0] & !a[0] & a[2] & !b[2] & b[1];
A1L83_p4_out = !b[0] & a[0] & !a[2] & b[2] & a[1];
A1L83 = A1L83_p0_out # A1L83_p1_out # A1L83_p2_out # A1L83_p3_out # A1L83_p4_out;


--A1L93 is reduce_or~2885
A1L93_p1_out = !b[1] & !b[0] & !a[0] & !a[1] & a[2] & !b[2];
A1L93_p2_out = !b[1] & !b[0] & !a[0] & !a[1] & !a[2] & b[2];
A1L93_p3_out = b[1] & !b[0] & !a[0] & a[1] & !a[2] & !b[2];
A1L93_p4_out = b[1] & b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L93 = A1L93_p1_out # A1L93_p2_out # A1L93_p3_out # A1L93_p4_out;


--A1L04 is reduce_or~2890
A1L04_p1_out = !a[0] & !a[1] & b[0] & !b[1];
A1L04 = A1L04_p1_out;


--A1L14 is reduce_or~2892
A1L14_p0_out = !a[2] & !a[0] & !a[1] & !b[1] & b[2];
A1L14_p1_out = !a[2] & !a[0] & b[0];
A1L14_p2_out = a[0] & !b[0] & !a[1] & !b[1];
A1L14_p3_out = !a[2] & a[0] & !b[0];
A1L14_p4_out = a[2] & !a[0] & !a[1] & !b[1] & !b[2];
A1L14 = A1L04 # A1L14_p0_out # A1L14_p1_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;


--A1L24 is reduce_or~2898
A1L24_p0_out = b[0] & b[1] & !a[2] & !b[2];
A1L24_p1_out = !b[0] & !a[0] & b[1] & a[2] & b[2];
A1L24_p2_out = b[0] & a[0] & a[2] & b[2] & a[1];
A1L24_p3_out = !b[0] & !a[0] & !b[1] & !a[2] & b[2];
A1L24_p4_out = !b[0] & !a[0] & !b[1] & a[2] & !b[2];
A1L24 = A1L24_p0_out # A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;


--A1L34 is reduce_or~2904
A1L34_p0_out = b[0] & b[1] & !a[2] & !a[1];
A1L34_p1_out = b[0] & !b[1] & a[2] & b[2];
A1L34_p2_out = b[1] & !a[2] & !b[2] & a[0];
A1L34_p3_out = !b[1] & a[2] & b[2] & a[0];
A1L34_p4_out = !b[0] & !b[1] & !a[0] & !a[1];
A1L34 = A1L24 # A1L34_p0_out # A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--A1L52 is reduce_or~2817sexp5
A1L52 = EXP(b[0] & a[0] & a[1]);


--A1L62 is reduce_or~2818bal
A1L62_p0_out = !b[2] & b[1] & a[1];
A1L62_p1_out = b[2] & a[2] & !b[1];
A1L62_p2_out = b[2] & a[2] & !a[1];
A1L62_p3_out = a[2] & !b[1] & !a[1];
A1L62_p4_out = a[2] & !b[0] & !a[0];
A1L62_or_out = A1L62_p0_out # A1L62_p1_out # A1L62_p2_out # A1L62_p3_out # A1L62_p4_out;
A1L62 = !(A1L62_or_out);


--A1L72 is reduce_or~2823bal
A1L72_p0_out = !b[1] & !a[1] & !b[0] & !a[0];
A1L72_p1_out = !a[2] & b[1] & a[1];
A1L72_p2_out = !b[1] & !a[1] & b[2];
A1L72_p3_out = b[1] & b[0] & a[0];
A1L72_p4_out = b[2] & !b[0] & !a[0];
A1L72_or_out = A1L72_p0_out # A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = !(A1L72_or_out);


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--c[0] is c[0]
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en is en
--operation mode is output

en = OUTPUT(~GND~0);


--c[1] is c[1]
--operation mode is output

c[1] = OUTPUT(A1L42);


--c[2] is c[2]
--operation mode is output

c[2] = OUTPUT(A1L82);


--c[4] is c[4]
--operation mode is output

c[4] = OUTPUT(A1L13);


--c[5] is c[5]
--operation mode is output

c[5] = OUTPUT(A1L23);


--c[7] is c[7]
--operation mode is output

c[7] = OUTPUT(A1L33);


--c[3] is c[3]
--operation mode is output

c[3] = OUTPUT(A1L43);


--c[6] is c[6]
--operation mode is output

c[6] = OUTPUT(A1L53);