📄 add.tan.rpt
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Timing Analyzer report for add
Sun Jan 11 21:29:23 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.265 ns ; a[0] ; c[6] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.265 ns ; a[0] ; c[6] ;
; N/A ; None ; 11.247 ns ; b[0] ; c[6] ;
; N/A ; None ; 11.246 ns ; a[0] ; c[3] ;
; N/A ; None ; 11.232 ns ; b[0] ; c[3] ;
; N/A ; None ; 11.195 ns ; b[0] ; c[7] ;
; N/A ; None ; 11.186 ns ; a[0] ; c[7] ;
; N/A ; None ; 11.136 ns ; b[0] ; c[5] ;
; N/A ; None ; 11.131 ns ; a[0] ; c[5] ;
; N/A ; None ; 11.131 ns ; a[0] ; c[2] ;
; N/A ; None ; 11.125 ns ; b[0] ; c[2] ;
; N/A ; None ; 11.110 ns ; a[0] ; c[4] ;
; N/A ; None ; 11.096 ns ; b[0] ; c[1] ;
; N/A ; None ; 11.092 ns ; b[0] ; c[4] ;
; N/A ; None ; 11.087 ns ; a[0] ; c[1] ;
; N/A ; None ; 11.060 ns ; a[1] ; c[6] ;
; N/A ; None ; 11.045 ns ; a[1] ; c[3] ;
; N/A ; None ; 11.008 ns ; a[1] ; c[7] ;
; N/A ; None ; 10.949 ns ; a[1] ; c[5] ;
; N/A ; None ; 10.938 ns ; a[1] ; c[2] ;
; N/A ; None ; 10.909 ns ; b[1] ; c[6] ;
; N/A ; None ; 10.909 ns ; a[1] ; c[1] ;
; N/A ; None ; 10.905 ns ; a[1] ; c[4] ;
; N/A ; None ; 10.890 ns ; b[1] ; c[3] ;
; N/A ; None ; 10.830 ns ; b[1] ; c[7] ;
; N/A ; None ; 10.775 ns ; b[1] ; c[5] ;
; N/A ; None ; 10.775 ns ; b[1] ; c[2] ;
; N/A ; None ; 10.754 ns ; b[1] ; c[4] ;
; N/A ; None ; 10.731 ns ; b[1] ; c[1] ;
; N/A ; None ; 10.352 ns ; b[2] ; c[6] ;
; N/A ; None ; 10.337 ns ; b[2] ; c[3] ;
; N/A ; None ; 10.300 ns ; b[2] ; c[7] ;
; N/A ; None ; 10.241 ns ; b[2] ; c[5] ;
; N/A ; None ; 10.230 ns ; b[2] ; c[2] ;
; N/A ; None ; 10.201 ns ; b[2] ; c[1] ;
; N/A ; None ; 10.197 ns ; b[2] ; c[4] ;
; N/A ; None ; 9.989 ns ; a[2] ; c[6] ;
; N/A ; None ; 9.974 ns ; a[2] ; c[3] ;
; N/A ; None ; 9.937 ns ; a[2] ; c[7] ;
; N/A ; None ; 9.878 ns ; a[2] ; c[5] ;
; N/A ; None ; 9.867 ns ; a[2] ; c[2] ;
; N/A ; None ; 9.838 ns ; a[2] ; c[1] ;
; N/A ; None ; 9.834 ns ; a[2] ; c[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:29:22 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[0]" to destination pin "c[6]" is 11.265 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 3; PIN Node = 'a[0]'
Info: 2: + IC(2.136 ns) + CELL(0.914 ns) = 4.182 ns; Loc. = LC_X2_Y1_N4; Fanout = 7; COMB Node = 'Add0~308'
Info: 3: + IC(1.335 ns) + CELL(0.740 ns) = 6.257 ns; Loc. = LC_X3_Y1_N5; Fanout = 1; COMB Node = 'WideOr1~4'
Info: 4: + IC(2.686 ns) + CELL(2.322 ns) = 11.265 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'c[6]'
Info: Total cell delay = 5.108 ns ( 45.34 % )
Info: Total interconnect delay = 6.157 ns ( 54.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jan 11 21:29:23 2009
Info: Elapsed time: 00:00:02
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