add.tan.qmsg

一些Verilog学习程序B

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 11 21:29:22 2009 " "Info: Processing started: Sun Jan 11 21:29:22 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off add -c add " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c\[6\] 11.265 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\[6\]\" is 11.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_27 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 3; PIN Node = 'a\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "add.v" "" { Text "E:/Verilog/基础实验/加法器/add.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.136 ns) + CELL(0.914 ns) 4.182 ns Add0~308 2 COMB LC_X2_Y1_N4 7 " "Info: 2: + IC(2.136 ns) + CELL(0.914 ns) = 4.182 ns; Loc. = LC_X2_Y1_N4; Fanout = 7; COMB Node = 'Add0~308'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.050 ns" { a[0] Add0~308 } "NODE_NAME" } } { "add.v" "" { Text "E:/Verilog/基础实验/加法器/add.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.740 ns) 6.257 ns WideOr1~4 3 COMB LC_X3_Y1_N5 1 " "Info: 3: + IC(1.335 ns) + CELL(0.740 ns) = 6.257 ns; Loc. = LC_X3_Y1_N5; Fanout = 1; COMB Node = 'WideOr1~4'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.075 ns" { Add0~308 WideOr1~4 } "NODE_NAME" } } { "add.v" "" { Text "E:/Verilog/基础实验/加法器/add.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.686 ns) + CELL(2.322 ns) 11.265 ns c\[6\] 4 PIN PIN_77 0 " "Info: 4: + IC(2.686 ns) + CELL(2.322 ns) = 11.265 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'c\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.008 ns" { WideOr1~4 c[6] } "NODE_NAME" } } { "add.v" "" { Text "E:/Verilog/基础实验/加法器/add.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.108 ns ( 45.34 % ) " "Info: Total cell delay = 5.108 ns ( 45.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.157 ns ( 54.66 % ) " "Info: Total interconnect delay = 6.157 ns ( 54.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.265 ns" { a[0] Add0~308 WideOr1~4 c[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.265 ns" { a[0] a[0]~combout Add0~308 WideOr1~4 c[6] } { 0.000ns 0.000ns 2.136ns 1.335ns 2.686ns } { 0.000ns 1.132ns 0.914ns 0.740ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 11 21:29:23 2009 " "Info: Processing ended: Sun Jan 11 21:29:23 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}