add.fit.eqn

一些Verilog学习程序B

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--A1L32 is reduce_or~2800 at SEXP109
A1L32 = EXP(a[2] & b[2] & !a[0]);


--A1L42 is reduce_or~2801 at SEXP108
A1L42 = EXP(!b[1] & !a[1]);


--A1L52 is reduce_or~2802 at SEXP107
A1L52 = EXP(!b[2] & !a[2]);


--A1L62 is reduce_or~2803 at SEXP106
A1L62 = EXP(b[2] & a[2]);


--A1L72 is reduce_or~2804 at SEXP98
A1L72 = EXP(b[1] & a[1]);


--A1L82 is reduce_or~2810 at LC99
A1L82_p0_out = a[2] & !b[0] & !a[0] & A1L72;
A1L82_p1_out = A1L32 & a[1] & b[1];
A1L82_p2_out = A1L42 & !a[2] & !b[2];
A1L82_p3_out = !a[1] & !b[1] & A1L52;
A1L82_p4_out = A1L62 & b[0] & a[0];
A1L82_or_out = A1L04 # A1L82_p0_out # A1L82_p1_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;
A1L82 = !(A1L82_or_out);


--A1L23 is reduce_or~2824 at LC86
A1L23_p1_out = A1L03 & A1L13 & A1L92;
A1L23_or_out = A1L23_p1_out;
A1L23 = A1L23_or_out;


--A1L33 is reduce_or~2831 at LC101
A1L33_p0_out = !b[0] & !a[0] & !a[1] & a[2] & b[2] & b[1];
A1L33_p1_out = !b[0] & a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L33_p2_out = b[0] & !a[0] & !a[1] & !a[2] & !b[2] & !b[1];
A1L33_p3_out = b[0] & !a[0] & a[1] & !a[2] & b[2];
A1L33_p4_out = !b[0] & !a[0] & a[1] & a[2] & b[2] & !b[1];
A1L33_or_out = A1L14 # A1L33_p0_out # A1L33_p1_out # A1L33_p2_out # A1L33_p3_out # A1L33_p4_out;
A1L33 = A1L33_or_out;


--A1L43 is reduce_or~2837 at LC103
A1L43_p0_out = b[0] & a[1] & !a[2] & b[2] & b[1];
A1L43_p1_out = !b[0] & a[0] & a[1] & a[2] & !b[2];
A1L43_p2_out = !b[0] & a[0] & a[2] & !b[2] & b[1];
A1L43_p3_out = b[0] & !a[1] & a[2] & b[2] & !b[1];
A1L43_p4_out = a[0] & !a[1] & a[2] & b[2] & !b[1];
A1L43_or_out = A1L24 # A1L43_p0_out # A1L43_p1_out # A1L43_p2_out # A1L43_p3_out # A1L43_p4_out;
A1L43 = A1L43_or_out;


--A1L53 is reduce_or~2839 at LC93
A1L53_p1_out = b[0] & a[1] & a[2] & !b[2] & b[1];
A1L53_or_out = A1L53_p1_out # A1L33 # A1L43;
A1L53 = A1L53_or_out;


--A1L63 is reduce_or~2848 at LC97
A1L63_p0_out = b[0] & a[0] & a[2] & b[2] & A1L42;
A1L63_p1_out = !b[0] & !a[0] & a[2] & b[2] & a[1] & b[1];
A1L63_p2_out = !b[0] & !a[0] & !a[2] & !b[2] & a[1] & !b[1];
A1L63_p3_out = !b[0] & !a[0] & !a[2] & !b[2] & !a[1] & b[1];
A1L63_p4_out = b[0] & a[0] & !a[2] & !b[2] & !a[1] & !b[1];
A1L63_or_out = A1L63_p0_out # A1L63_p1_out # A1L63_p2_out # A1L63_p3_out # A1L63_p4_out;
A1L63 = A1L63_or_out;


--A1L73 is reduce_or~2855 at LC88
A1L73_p0_out = !b[0] & a[0] & a[2] & b[2] & A1L84;
A1L73_p1_out = !b[1] & b[0] & a[0] & a[1] & !a[2] & !b[2];
A1L73_p2_out = !b[1] & !b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L73_p3_out = !b[1] & b[0] & !a[0] & !a[1] & !a[2] & !b[2];
A1L73_p4_out = b[0] & !a[0] & a[2] & b[2] & A1L84;
A1L73_or_out = A1L34 # A1L73_p0_out # A1L73_p1_out # A1L73_p2_out # A1L73_p3_out # A1L73_p4_out;
A1L73 = A1L73_or_out;


--A1L83 is reduce_or~2861 at LC91
A1L83_p0_out = !b[2] & !a[0] & b[0];
A1L83_p1_out = !a[2] & !b[2] & !a[0] & a[1] & b[1];
A1L83_p2_out = !a[2] & !b[2] & !a[1] & b[1] & b[0];
A1L83_p3_out = !a[2] & !b[2] & a[1] & !b[1] & b[0];
A1L83_p4_out = !b[2] & a[0] & !b[0];
A1L83_or_out = A1L54 # A1L83_p0_out # A1L83_p1_out # A1L83_p2_out # A1L83_p3_out # A1L83_p4_out;
A1L83 = A1L83_or_out;


--A1L93 is reduce_or~2862 at LC85
A1L93_p0_out = !a[2] & !a[1] & !b[2];
A1L93_p2_out = a[0] & b[1] & !a[2] & !a[1];
A1L93_p3_out = b[1] & !a[1] & b[0] & !b[2];
A1L93_p4_out = a[0] & b[1] & !a[1] & !b[2];
A1L93_or_out = A1L74 # A1L93_p0_out # A1L93_p2_out # A1L93_p3_out # A1L93_p4_out;
A1L93 = !a[1] $ A1L93_or_out;


--A1L04 is reduce_or~2869 at LC98
A1L04_p1_out = !a[2] & !b[0] & !a[0] & b[2];
A1L04_p2_out = a[2] & b[0] & !a[0] & b[2];
A1L04_p3_out = a[2] & !b[0] & a[0] & b[2];
A1L04 = A1L04_p1_out # A1L04_p2_out # A1L04_p3_out;


--A1L14 is reduce_or~2873 at LC100
A1L14_p0_out = b[0] & a[0] & a[1] & !a[2] & !b[2] & !b[1];
A1L14_p1_out = !b[0] & !a[0] & !a[1] & a[2] & !b[2] & !b[1];
A1L14_p2_out = !b[0] & !a[0] & !a[1] & !a[2] & b[2] & !b[1];
A1L14_p3_out = !b[0] & !a[0] & a[1] & !a[2] & !b[2] & b[1];
A1L14_p4_out = b[0] & a[0] & !a[1] & !a[2] & !b[2] & b[1];
A1L14 = A1L14_p0_out # A1L14_p1_out # A1L14_p2_out # A1L14_p3_out # A1L14_p4_out;


--A1L24 is reduce_or~2879 at LC102
A1L24_p0_out = !b[0] & a[0] & !a[2] & b[2] & b[1];
A1L24_p1_out = b[0] & !a[0] & !a[2] & b[2] & b[1];
A1L24_p2_out = b[0] & !a[0] & a[2] & !b[2] & a[1];
A1L24_p3_out = b[0] & !a[0] & a[2] & !b[2] & b[1];
A1L24_p4_out = !b[0] & a[0] & !a[2] & b[2] & a[1];
A1L24 = A1L24_p0_out # A1L24_p1_out # A1L24_p2_out # A1L24_p3_out # A1L24_p4_out;


--A1L34 is reduce_or~2885 at LC87
A1L34_p1_out = !b[1] & !b[0] & !a[0] & !a[1] & a[2] & !b[2];
A1L34_p2_out = !b[1] & !b[0] & !a[0] & !a[1] & !a[2] & b[2];
A1L34_p3_out = b[1] & !b[0] & !a[0] & a[1] & !a[2] & !b[2];
A1L34_p4_out = b[1] & b[0] & a[0] & !a[1] & !a[2] & !b[2];
A1L34 = A1L34_p1_out # A1L34_p2_out # A1L34_p3_out # A1L34_p4_out;


--A1L44 is reduce_or~2890 at LC89
A1L44_p1_out = !a[0] & !a[1] & b[0] & !b[1];
A1L44 = A1L44_p1_out;


--A1L54 is reduce_or~2892 at LC90
A1L54_p0_out = !a[2] & !a[0] & !a[1] & !b[1] & b[2];
A1L54_p1_out = !a[2] & !a[0] & b[0];
A1L54_p2_out = a[0] & !b[0] & !a[1] & !b[1];
A1L54_p3_out = !a[2] & a[0] & !b[0];
A1L54_p4_out = a[2] & !a[0] & !a[1] & !b[1] & !b[2];
A1L54 = A1L44 # A1L54_p0_out # A1L54_p1_out # A1L54_p2_out # A1L54_p3_out # A1L54_p4_out;


--A1L64 is reduce_or~2898 at LC83
A1L64_p0_out = b[0] & b[1] & !a[2] & !b[2];
A1L64_p1_out = !b[0] & !a[0] & b[1] & a[2] & b[2];
A1L64_p2_out = b[0] & a[0] & a[2] & b[2] & a[1];
A1L64_p3_out = !b[0] & !a[0] & !b[1] & !a[2] & b[2];
A1L64_p4_out = !b[0] & !a[0] & !b[1] & a[2] & !b[2];
A1L64 = A1L64_p0_out # A1L64_p1_out # A1L64_p2_out # A1L64_p3_out # A1L64_p4_out;


--A1L74 is reduce_or~2904 at LC84
A1L74_p0_out = b[0] & b[1] & !a[2] & !a[1];
A1L74_p1_out = b[0] & !b[1] & a[2] & b[2];
A1L74_p2_out = b[1] & !a[2] & !b[2] & a[0];
A1L74_p3_out = !b[1] & a[2] & b[2] & a[0];
A1L74_p4_out = !b[0] & !b[1] & !a[0] & !a[1];
A1L74 = A1L64 # A1L74_p0_out # A1L74_p1_out # A1L74_p2_out # A1L74_p3_out # A1L74_p4_out;


--~VCC~0 is ~VCC~0 at LC94
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~GND~0 is ~GND~0 at LC118
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;


--A1L92 is reduce_or~2817sexp5 at SEXP87
A1L92 = EXP(b[0] & a[0] & a[1]);


--A1L03 is reduce_or~2818bal at LC105
A1L03_p0_out = !b[2] & b[1] & a[1];
A1L03_p1_out = b[2] & a[2] & !b[1];
A1L03_p2_out = b[2] & a[2] & !a[1];
A1L03_p3_out = a[2] & !b[1] & !a[1];
A1L03_p4_out = a[2] & !b[0] & !a[0];
A1L03_or_out = A1L03_p0_out # A1L03_p1_out # A1L03_p2_out # A1L03_p3_out # A1L03_p4_out;
A1L03 = !(A1L03_or_out);


--A1L13 is reduce_or~2823bal at LC104
A1L13_p0_out = !b[1] & !a[1] & !b[0] & !a[0];
A1L13_p1_out = !a[2] & b[1] & a[1];
A1L13_p2_out = !b[1] & !a[1] & b[2];
A1L13_p3_out = b[1] & b[0] & a[0];
A1L13_p4_out = b[2] & !b[0] & !a[0];
A1L13_or_out = A1L13_p0_out # A1L13_p1_out # A1L13_p2_out # A1L13_p3_out # A1L13_p4_out;
A1L13 = !(A1L13_or_out);


--a[0] is a[0] at PIN_24
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_22
--operation mode is input

a[1] = INPUT();


--a[2] is a[2] at PIN_21
--operation mode is input

a[2] = INPUT();


--b[0] is b[0] at PIN_20
--operation mode is input

b[0] = INPUT();


--b[1] is b[1] at PIN_18
--operation mode is input

b[1] = INPUT();


--b[2] is b[2] at PIN_17
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_61
--operation mode is output

c[0] = OUTPUT(~VCC~0);


--en is en at PIN_75
--operation mode is output

en = OUTPUT(~GND~0);


--c[1] is c[1] at PIN_64
--operation mode is output

c[1] = OUTPUT(A1L82);


--c[2] is c[2] at PIN_56
--operation mode is output

c[2] = OUTPUT(A1L23);


--c[4] is c[4] at PIN_60
--operation mode is output

c[4] = OUTPUT(A1L53);


--c[5] is c[5] at PIN_63
--operation mode is output

c[5] = OUTPUT(A1L63);


--c[7] is c[7] at PIN_57
--operation mode is output

c[7] = OUTPUT(A1L73);


--c[3] is c[3] at PIN_58
--operation mode is output

c[3] = OUTPUT(A1L83);


--c[6] is c[6] at PIN_55
--operation mode is output

c[6] = OUTPUT(A1L93);






--A1L84 is reduce_or~2910 at SEXP86
A1L84 = EXP(!b[1] & !a[1]);